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firrtl interpreter is an experimental circuit simulator that executes low Firrtl IR.\nIt is one of the standard back-ends available as part of the [chisel-testers](https://github.com/ucb-bar/chisel-testers.git) project, \nand thus one of the tools in the [UCB-BAR/chisel](https://github.com/ucb-bar) hardware synthesis toolbox. \nThis project provides a test harness supporting a peek, poke expect model.  \nIt also provides a interactive simulator shell or repl (see frepl.sh) that allows fine grained incremental execution of\n a circuit. \nIn combination with a scala debugger such as Eclipse or IntelliJ it can be a very power way of analyzing problematic\nbehavior.  The interpreter has not yet been optimzed for performance and may be too slow for emulation of very complex\ncircuits.\n\n[Chisel3](https://github.com/ucb-bar/chisel3.git) is a high-level functional circuit generator. It produces **Flexible Intermediate\nRepresentation for RTL** or **FIRRTL**.  The [Firrtl](https://github.com/ucb-bar/firrtl.git) project parses and\ntransforms firrtl.  It also provides mechanisms for emitting verilog, for processing by downstream toolchains.\nThis interpreter parse and execute the LoFirrtl subset of Firrtl. The interpreter is useful for a initial debugging of Chisel circuits\nand is also used for other forms of circuit analysis. \n\n## Using the interpreter\n### Attach it to your project\nMost Chisel development projects will have a an SBT file that describes dependencies. To access the firrtl-interpreter in your project\nadd a dependency on\n```\n\"edu.berkeley.cs\" %% \"firrtl-interpreter\" % \"0.1-SNAPSHOT\"\n```\nThere are a number of different ways to specify this dependency in the build.sbt file. If you have based your circuit on the \n[Chisel-template](https://github.com/ucb-bar/chisel-template.git) the addition should look like\n```scala\nlibraryDependencies ++= Seq(\n  \"edu.berkeley.cs\" %% \"chisel3\" % chiselVersion,\n  \"edu.berkeley.cs\" %% \"chisel-iotesters\" % \"1.0\",\n  \"edu.berkeley.cs\" %% \"firrtl-interpreter\" % \"0.1-SNAPSHOT\",\n  \"org.scalatest\" % \"scalatest_2.11\" % \"2.2.4\",\n  \"org.scalacheck\" %% \"scalacheck\" % \"1.12.4\")\n```\nfor other usage consult **sbt** documentation\n\n### Use the tester metaphor\nThe easiest way to invoke the interpreter is through a test based harness. The InterpretiveTester is very similar to the chisel\nClassicTester, it's api consists of poke, peek and expect statements. Here is an example of a GCD Circuit\n\n```scala\nimport Chisel._\nimport firrtl_interpreter.InterpretiveTester\nimport org.scalatest.{Matchers, FlatSpec}\n\nobject GCDCalculator {\n  def computeGcd(a: Int, b: Int): (Int, Int) = {\n    var x = a\n    var y = b\n    var depth = 1\n    while(y \u003e 0 ) {\n      if (x \u003e y) {\n        x -= y\n      }\n      else {\n        y -= x\n      }\n      depth += 1\n    }\n    (x, depth)\n  }\n}\n\nclass GCD extends Module {\n  val io = new Bundle {\n    val a  = UInt(INPUT,  16)\n    val b  = UInt(INPUT,  16)\n    val e  = Bool(INPUT)\n    val z  = UInt(OUTPUT, 16)\n    val v  = Bool(OUTPUT)\n  }\n  val x  = Reg(UInt())\n  val y  = Reg(UInt())\n  when   (x \u003e y) { x := x - y }\n  unless (x \u003e y) { y := y - x }\n  when (io.e) { x := io.a; y := io.b }\n  io.z := x\n  io.v := y === UInt(0)\n}\n\n\nclass InterpreterUsageSpec extends FlatSpec with Matchers {\n\n  \"GCD\" should \"return correct values for a range of inputs\" in {\n    val s = Driver.emit(() =\u003e new GCD)\n\n    val tester = new InterpretiveTester(s)\n\n    for {\n      i \u003c- 1 to 100\n      j \u003c- 1 to 100\n    } {\n      tester.poke(\"io_a\", i)\n      tester.poke(\"io_b\", j)\n      tester.poke(\"io_e\", 1)\n      tester.step()\n      tester.poke(\"io_e\", 0)\n\n      var cycles = 0\n      while (tester.peek(\"io_v\") != BigInt(1)) {\n        tester.step()\n        cycles += 1\n      }\n      tester.expect(\"io_z\", BigInt(GCDCalculator.computeGcd(i, j)._1))\n      // uncomment the println to see a lot of output\n      // println(f\"GCD(${i}%3d, ${j}%3d) =\u003e ${interpretiveTester.peek(\"io_z\")}%3d in $cycles%3d cycles\")\n    }\n    tester.report()\n  }\n}\n```\n\n### About ports and names\nThe firrtl transformations that result in LoFirrtl alter the names of ports.  What would be io.a becomes io_a and so forth.\n\n### Using the interpreter with a debugger\nThis section under development\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffreechipsproject%2Ffirrtl-interpreter","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffreechipsproject%2Ffirrtl-interpreter","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffreechipsproject%2Ffirrtl-interpreter/lists"}