{"id":13416912,"url":"https://github.com/frwang96/verik","last_synced_at":"2026-01-14T02:03:44.091Z","repository":{"id":40385693,"uuid":"269980078","full_name":"frwang96/verik","owner":"frwang96","description":"Verik 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HDL and Transpilers","Circuit Compilers"],"sub_categories":[],"readme":"[![Maven](https://img.shields.io/github/v/release/frwang96/verik)](\nhttps://search.maven.org/search?q=io.verik)\n[![License](https://img.shields.io/github/license/frwang96/verik)](\nhttps://opensource.org/licenses/Apache-2.0)\n\n\nVerik is a hardware description language (HDL) for designing and verifying digital integrated circuits.\nThe goal of Verik is to enable the modern IDE workflow to bridge the technology gap between hardware and software\ndevelopment.\nVerik aims to be a drop-in replacement for SystemVerilog.\nIt leverages the productivity of the modern software stack to enable faster onboarding, shorter schedules, and reduced\nengineering costs.\nVerik builds upon [Kotlin](https://kotlinlang.org), a modern general-purpose programming language with a clean and\nexpressive syntax.\nVerik is Kotlin reinterpreted with the semantics of an HDL.\nIt can directly make use of tools built for the vibrant Kotlin ecosystem, such as the widely used\n[IntelliJ IDEA IDE](https://www.jetbrains.com/idea/).\nVerik is translated to SystemVerilog by the Verik compiler.\nThis translation process is direct, typically with one-to-one correspondence between the input and output source files.\nVerik generates readable SystemVerilog similar to what an engineer would have written.\n\nThe Verik toolchain connects the Kotlin and SystemVerilog environments.\nThe Verik compiler translates Verik source code into SystemVerilog.\nHowever, we can also go in the other direction.\nIf we had SystemVerilog source code that we would like to reference from the Kotlin environment, the Verik importer can\nbe used to import the declaration headers.\nThis allows us to make use of SystemVerilog libraries such as the\n[UVM](https://www.accellera.org/downloads/standards/uvm) directly in Verik.\nIt also enables us to benefit from the productivity improvements of Verik without having to rewrite any legacy code.\n\nFor examples of Verik projects refer to [examples](https://github.com/frwang96/verik-examples).\nFor a template project refer to [template](https://github.com/frwang96/verik-template).\n\nVerik is an open source project under the Apache License, Version 2.0.\nIt was initially developed as a master's thesis project at the Massachusetts Institute of Technology.\n\n## Local Build\n\nVerik releases are published through [maven central](https://search.maven.org/search?q=io.verik).\nTo build the toolchain locally from source clone this repository and execute the `mainInstall` gradle task.\n\n```\ngit clone https://github.com/frwang96/verik\ncd verik\n./gradlew mainInstall\n```\n\nTo reference the local build in a project, set the version of the plugin in `build.gradle.kts` to `local-SNAPSHOT`.\n\n```kotlin\nplugins {\n    id(\"io.verik.verik-plugin\") version \"local-SNAPSHOT\"\n}\n```\n\n## Gradle Tasks\n\nVerik makes use of [gradle](https://gradle.org) for build automation.\nHere are the main gradle tasks for the project.\nEach module also defines its own tasks for building, testing, and reformatting.\nThese can be accessed from the Gradle toolbar.\n\n- `mainCheck`: Run the tests and lint checks.\n- `mainClean`: Clean all build directories.\n- `mainFormat`: Reformat the source code.\n- `mainGenerate`: Run the ANTLR parser generator for the importer.\n- `mainInstall`: Install the gradle plugin.\n- `mainTest`: Run the tests.\n- `mainVerik`: Run the toolchain on the sandbox project.\n- `mainVerikCompile`: Run the compiler on the sandbox project.\n- `mainVerikImport`: Run the importer on the sandbox project.\n\n## Gradle Modules\n\nThe Verik toolchain is structured as a gradle composite build.\nThe final output of the build is a [gradle plugin](https://plugins.gradle.org/plugin/io.verik.verik-plugin) that\npackages the importer and compiler, allowing them to be run as gradle tasks in Verik projects.\nThe project consists of the following gradle modules.\n\n### verik-kotlin\nDocumentation for declarations from the Kotlin standard library that are shared with Verik.\nThis is used to generate part of the API doc but are not used anywhere else in the toolchain.\n\n### verik-core\nThe core library that is imported in all Verik projects that is used to express HDL semantics.\nThe Verik compiler and importer recognize these as built-in declarations.\n\n### verik-importer\nThe importer that brings in SystemVerilog declarations to be used in Verik projects. \nThe importer parses SystemVerilog source files with [ANTLR](https://www.antlr.org) and executes a sequence of stages\nto convert the syntax trees to Verik.\n\n### verik-compiler\nThe compiler that generates SystemVerilog output from Verik source files.\nThe compiler first runs the Kotlin compiler front-end and extracts its intermediate syntax tree representation.\nIt then executes a sequence of stages to convert the syntax trees to SystemVerilog.\n\n### verik-plugin\nThe gradle plugin that packages the importer and compiler.\nIt configures the toolchain based on the `verik` block that is specified in `build.gradle.kts`.\n\n### verik-sandbox\nA sandbox project that can be used for quick development and debugging.\nThe toolchain is automatically recompiled when the sandbox project is run, so there is no need to execute `mainInstall`.\nVerilog or SystemVerilog source code to be imported should be placed under `verik-sandbox/src/main/verilog` and Verik\nsource code to be compiled should be placed under `verik-sandbox/src/main/kotlin`.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffrwang96%2Fverik","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffrwang96%2Fverik","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffrwang96%2Fverik/lists"}