{"id":36627967,"url":"https://github.com/fujitsu/xbyak_aarch64","last_synced_at":"2026-01-12T09:34:14.609Z","repository":{"id":37414479,"uuid":"226821787","full_name":"fujitsu/xbyak_aarch64","owner":"fujitsu","description":null,"archived":false,"fork":false,"pushed_at":"2025-04-05T04:01:05.000Z","size":2125,"stargazers_count":199,"open_issues_count":9,"forks_count":41,"subscribers_count":24,"default_branch":"main","last_synced_at":"2025-04-05T05:18:28.435Z","etag":null,"topics":["aarch","jit-assembler","sve","xbyak"],"latest_commit_sha":null,"homepage":null,"language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/fujitsu.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-12-09T08:28:23.000Z","updated_at":"2025-04-05T04:01:10.000Z","dependencies_parsed_at":"2023-02-18T22:15:49.542Z","dependency_job_id":"992842af-72a7-4342-b140-7409342e200c","html_url":"https://github.com/fujitsu/xbyak_aarch64","commit_stats":null,"previous_names":[],"tags_count":6,"template":false,"template_full_name":null,"purl":"pkg:github/fujitsu/xbyak_aarch64","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fujitsu%2Fxbyak_aarch64","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fujitsu%2Fxbyak_aarch64/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fujitsu%2Fxbyak_aarch64/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fujitsu%2Fxbyak_aarch64/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/fujitsu","download_url":"https://codeload.github.com/fujitsu/xbyak_aarch64/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/fujitsu%2Fxbyak_aarch64/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28337728,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-12T06:09:07.588Z","status":"ssl_error","status_checked_at":"2026-01-12T06:05:18.301Z","response_time":98,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["aarch","jit-assembler","sve","xbyak"],"created_at":"2026-01-12T09:34:14.548Z","updated_at":"2026-01-12T09:34:14.600Z","avatar_url":"https://github.com/fujitsu.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"[![Build Status](https://travis-ci.org/herumi/xbyak_aarch64.png)](https://travis-ci.org/herumi/xbyak_aarch64)\n\n# Xbyak_aarch64 ; JIT assembler for AArch64 CPUs by C++\n\n## Abstract\n\nXbyak_aarch64 is a C++ library which enables run-time assemble coding with the AArch64 instruction set of Arm(R)v8-A architecture.\nXbyak_aarch64 is based on Xbyak developed for x86_64 CPUs by MITSUNARI Shigeo.\n\n## Feature\n\n* GNU assembler like syntax.\n* Fully support SVE instructions.\n\n### Requirement\n\nXbyak_aarch64 uses no external library and it is written as standard C++ files\nso that we believe Xbyak_aarch64 works various environment with various compilers.\n\n### News\nBreak backward compatibility:\n- To link `libxbyak_aarch64.a` is always necessary.\n- namespace `Xbyak` is renamed to `Xbyak_aarch64`.\n- Some class are renamed (e.g. CodeGeneratorAArch64 -\u003e CodeGenerator).\n- L_aarch64() is renamed to L().\n- use dd(uint32_t) instead of dw(uint32_t).\n\n### Supported Compilers\n\nAlmost C++11 or later compilers for AArch64 such as g++, clang++.\n\n## Install\n\nThe command `make` builds `lib/libxbyak_aarch64.a`.\n\n`make install` installs headers and a library into `/usr/local/` (default path).\nOr add the location of the `xbyak_aarch64` directory to your compiler's include and link paths.\n\n### Execution environment\n\nYou can execute programs using xbyak_aarch64 on systems running on Arm(R)v8-A architecure CPUs.\nEven if you can't access such systems, you can try Xbyak_aarch64 on QEMU (generic and open source machine emulator and virtualizer).\n\nWe have checked programs built with xbyak_aarch64 can be executed with qemu version 3.1.0 on Linux running on x86_64 CPUs.\nThe following dpkgs are required.\n\n* binutils-aarch64-linux-gnu\n* cpp-8-aarch64-linux-gnu\n* cpp-aarch64-linux-gnu\n* g++-8-aarch64-linux-gnu\n* g++-aarch64-linux-gnu\n* gcc-8-aarch64-linux-gnu\n* gcc-8-aarch64-linux-gnu-base:amd64\n* gcc-aarch64-linux-gnu\n* pkg-config-aarch64-linux-gnu\n* qemu\n* qemu-block-extra:amd64\n* qemu-system-arm\n* qemu-system-common\n* qemu-system-data\n* qemu-system-gui\n* qemu-user\n* qemu-user-static\n* qemu-utils\n\n\nThen execute the following commands.\n```\ncd xbyak_aarch64/sample\naarch64-linux-gnu-g++ add.cpp\nenv QEMU_LD_PREFIX=/usr/aarch64-linux-gnu qemu-aarch64 ./a.out\n```\n\nOn Fedora linux use\n```\nsudo dnf install qemu qemu-user qemu-system-aarch64 qemu-user-static-aarch64\nmake clean\nCXX=aarch64-redhat-linux-g++ make\ncd sample\nCXX=aarch64-redhat-linux-g++ make\naarch64-redhat-linux-g++ add.cpp -I ../ -L../lib/libxbyak_aarch64.a\n```\n\n## M1 mac\nFor test, aarch64-gas is necessary.\nMake the binary from [GNU-A Downloads](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads) or use [aarch64-unknown-linux-gnu](https://github.com/thinkski/osx-arm-linux-toolchains).\n\n## How to make lib\n\n```\nmake\n```\nmakes `lib/libxbyak_aarch64.a`.\n\n## How to use cmake\n\non Windows ARM64\n```\nmkdir build\ncd build\ncmake .. -A arm64\nmsbuild xbyak_aarch64.sln /p:Configuration=Release\n```\n\n## How to use Xbyak_aarch64\n\nInherit `Xbyak::CodeGenerator` class and make the class method.\nMake an instance of the class and get the function\npointer by calling `getCode()` and call it.\nThe following example 1) generates a JIT-ed function which simply adds two integer values passed as arguments and returns an integer value as a result,\nand 2) calls the function. This example outputs \"7\" to STDOUT.\n\ncompile options:\n- `-I \u003cxbyak_aarch64 dir\u003e/xbyak_aarch64`.\n- `-L \u003cxbyak_aarch64 dir\u003e/lib -lxbyak_aarch64`.\n\n```\n#include \"xbyak_aarch64.h\"\nusing namespace Xbyak_aarch64;\nclass Generator : public CodeGenerator {\npublic:\n  Generator() {\n    Label L1, L2;\n    L(L1);\n    add(w0, w1, w0);\n    cmp(w0, 13);\n    b(EQ, L2);\n    sub(w1, w1, 1);\n    b(L1);\n    L(L2);\n    ret();\n  }\n};\nint main() {\n  Generator gen;\n  gen.ready();\n  auto f = gen.getCode\u003cint (*)(int, int)\u003e();\n  std::cout \u003c\u003c f(3, 4) \u003c\u003c std::endl;\n  return 0;\n}\n```\n\n## Syntax\nSynatx is similar to \"AS\" (GNU assembler).\nEach AArch64 instruction is correspond to each function written in \"xbyak_aarch64_mnemonic.h\", we call it a **mnemonic function**.\nPlease refer files in sample/mnemonic_syntax directory for usage of mnemonic functions.\nThe below example shows correspondence between \"AS\" syntax and Xbyak_aarch64 mnemonic functions.\n\n```\n\"AS\"                  Xbyak_aarch64\nadd w0, w0, w1  --\u003e add(w0, w0, w1);\nadd x0, x0, x1  --\u003e add(x0, x0, x1);\nadd x0, x0, 5   --\u003e add(x0, x0, 5);\nmov w0, 1       --\u003e mov(w0, 1);\nret             --\u003e ret();\n```\n\n### Mnemonic functions\nEach **mnemonic function** corresponds to one AArch64 instruction.\nFunction name represents corresponding mnemonic of instruction.\nBecause **\"and\", \"or\", \"not\"** are reserved keywords C++ and **\".\"** can't be used in C++ function name,\nthe following special cases are exist.\n\n|Mnemonic of instruction|Name of **mnemonic funciton**|\n|----|----|\n|and|and_|\n|or|or_|\n|not|not_|\n|b.cond|b|\n\n### Operand\nThis section explains operands, which are given to mnemonic functions as their arguments.\n\n#### General purpose registers\n\nAs general purpose registers,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|w0, w1, ..., w30|WReg|32-bit general purpose registers|\n|x0, x1, ..., x30|WReg|64-bit general purpose registers|\n|wzr|WReg|32-bit zero register|\n|xzr|XReg|64-bit zero register|\n|wsp|WReg|32-bit stack pointer|\n|sp|zXReg|64-bit stack pointer|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nWReg dstReg(0);\nWReg srcReg0(1);\nWReg srcReg1(2);\n\nadd(dstReg, srcReg0, srcReg1);  \u003c--- (1)\nadd(w0, w1, w2);                \u003c--- Output is same JIT code of (1)\n```\n\n##### SIMD/Floating point registers as scalar registers\n\nAs SIMD/Floating point registers with scalar use,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|b0, b1, ..., b31|BReg|8-bit scalar registers|\n|h0, h1, ..., h31|HReg|16-bit scalar registers|\n|s0, s1, ..., s31|SReg|32-bit scalar registers|\n|d0, d1, ..., d31|DReg|64-bit scalar registers|\n|q0, q1, ..., q31|QReg|128-bit scalar registers|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nBReg dstReg(0);\n\nmov(b0, v0.b[5]);       \u003c--- (1)\nmov(dstReg, v0.b[5]);   \u003c--- Output is same JIT code of (1)\n\n```\n\n#### SIMD/Floating point registers as vector registers\n\nAs SIMD/Floating point registers with vector use,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|v0.b8, v1.b8, ..., v31.b8|VReg8B|8-bit x8 elements vector registers|\n|v0.b16, v1.b16, ..., v31.b16|VReg16B|8-bit x16 elements vector registers|\n|v0.h4, v1.h4, ..., v31.h4|VReg4H|16-bit x4 elements vector registers|\n|v0.h8, v1.h8, ..., v31.h8|VReg8H|16-bit x8 elements vector registers|\n|v0.s2, v1.s2, ..., v31.s2|VReg2S|32-bit x2 elements vector registers|\n|v0.s4, v1.s4, ..., v31.s4|VReg4S|32-bit x4 elements vector registers|\n|v0.d1, v1.d1, ..., v31.d1|VReg1D|64-bit x1 elements vector registers|\n|v0.d2, v1.d2, ..., v31.d2|VReg2D|64-bit x2 elements vector registers|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nVReg16B dstReg(0);\nVReg16B srcReg(1);\n\nmov(v0.b16, v1.b16);   \u003c--- (1)\nmov(dstReg, srcReg);   \u003c--- Output is same JIT code of (1)\n```\n\n#### Element of SIMD/Floating point registers\n\nAs SIMD/Floating point registers with element-wise use,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|v0.b[0], v0.b[1], ..., v0.b[15]|VRegBElem|8-bit element of vector register #0|\n|vN.b[0], vN.b[1], ..., vN.b[15]|VRegBElem|8-bit element of vector register #N|\n|v0.h[0], v0.h[1], ..., v0.h[15]|VRegHElem|16-bit element of vector register #0|\n|vN.h[0], vN.h[1], ..., vN.h[15]|VRegHElem|16-bit element of vector register #N|\n|v0.s[0], v0.s[1], ..., v0.s[15]|VRegSElem|32-bit element of vector register #0|\n|vN.s[0], vN.s[1], ..., vN.s[15]|VRegSElem|32-bit element of vector register #N|\n|v0.d[0], v0.d[1], ..., v0.d[15]|VRegDElem|64-bit element of vector register #0|\n|vN.d[0], vN.d[1], ..., vN.d[15]|VRegDElem|64-bit element of vector register #N|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nVRegBElem dstReg(0, 3, 16);\nVRegBElem srcReg(1, 4, 16);\nVRegB     hoge(0);\n\nmov(v0.b[3], v1.b[4]); \u003c--- (1)\nmov(dstReg,  srcReg);  \u003c--- Output is same JIT code of (1)\nmov(hoge[3], srcReg);  \u003c--- Output is same JIT code of (1)\n```\n\n### SIMD/Floating point register lists\n\nAs SIMD/Floating point register lists,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\nRegister index can be cyclic.\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|v0.b16 - v0.b16|VReg16BList|SIMD/Floating point register list containing 8-bit elements x 16 x 1|\n|v0.b16 - v1.b16|VReg16BList|SIMD/Floating point register list containing 8-bit elements x 16 x 2|\n|v0.b16 - v2.b16|VReg16BList|SIMD/Floating point register list containing 8-bit elements x 16 x 3|\n|v0.b16 - v3.b16|VReg16BList|SIMD/Floating point register list containing 8-bit elements x 16 x 4|\n|v31.b16 - v2.b16|VReg16BList|SIMD/Floating point register list containing 8-bit elements x 16 x 4|\n|v0.h8 - v3.h8|VReg8HList|SIMD/Floating point register list containing 16-bit elements x 8 x 4|\n|v0.s4 - v3.s4|VReg4SList|SIMD/Floating point register list containing 32-bit elements x 4 x 4|\n|v0.d2 - v3.d2|VReg2DList|SIMD/Floating point register list containing 64-bit elements x 2 x 4|\n\nYou can also use your original instance as mnemonic functions arguments.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nVReg16BList dstList(v0.b16, v3.b16);\nVReg16BList hoge(VReg16B(0), VReg16B(3));\n\nld4((v0.b16 - v3.b16), ptr(x0)); \u003c--- (1)\nld4(dstLsit, ptr(x0));   \u003c--- Output is same JIT code of (1)\nld4(hoge, ptr(x0));      \u003c--- Output is same JIT code of (1)\n\n```\n\n### Element of vector register lists\n\nAs elements of SIMD/Floating point register lists,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|(v0.b16 - v0.b16)[0]|VRegBElem|First 8-bit element of one-vector-register list|\n|(v0.b16 - v0.b16)[N]|VRegBElem|N-th 8-bit element of one-vector-register list|\n|(v0.b16 - v3.b16)[N]|VRegBElem|N-th 8-bit element of four-vector-register list|\n|(v0.h8 - v3.h8)[N]|VRegHElem|N-th 16-bit element of four-vector-register list|\n|(v0.s4 - v3.s4)[N]|VRegSElem|N-th 32-bit element of four-vector-register list|\n|(v0.d2 - v3.d2)[N]|VRegDElem|N-th 64-bit element of four-vector-register list|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nVRegBElem dstReg(0, 3, 16);\nVRegBElem hoge((VReg16B(0) - VReg16B(3))[3]);\n\nld4((v0.b16 - v3.b16)[3], ptr(x0)); \u003c--- (1)\nld4(dstReg, ptr(x0));       \u003c--- Output is same JIT code of (1)\nld4(hoge, ptr(x0));         \u003c--- Output is same JIT code of (1)\n\n```\n\n### SVE registers as vector registers\nAS SVE registers,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|Z0.b, z1.b, ..., z31.b|ZRegB|8-bit x 64 elements SVE registers.|\n|Z0.h, z1.h, ..., z31.h|ZRegB|16-bit x 32 elements SVE registers.|\n|Z0.s, z1.s, ..., z31.s|ZRegB|32-bit x 16 elements SVE registers.|\n|Z0.d, z1.d, ..., z31.d|ZRegB|64-bit x 8 elements SVE registers.|\n|Z0.q, z1.q, ..., z31.q|ZRegB|128-bit x 4 elements SVE registers.|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nZRegB dstReg(0);\n\nadd(z0.b, z1.b, z2.b);      \u003c--- (1)\nadd(ZRegB(0), z1.b, z2.b);  \u003c--- Output is same JIT code of (1)\nadd(dstReg, z1.b, z2.b);    \u003c--- Output is same JIT code of (1)\n\n```\n\n### Element of SVE registers\n\nAs SVE registers with element-wise use,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|z0.b[0], z0.b[1], ..., z0.b[15]|ZRegBElem|8-bit element of SVE register #0|\n|vN.b[0], vN.b[1], ..., vN.b[15]|ZRegBElem|8-bit element of SVE register #N|\n|z0.h[0], z0.h[1], ..., z0.h[15]|ZRegHElem|16-bit element of SVE register #0|\n|vN.h[0], vN.h[1], ..., vN.h[15]|ZRegHElem|16-bit element of SVE register #N|\n|z0.s[0], z0.s[1], ..., z0.s[15]|ZRegSElem|32-bit element of SVE register #0|\n|vN.s[0], vN.s[1], ..., vN.s[15]|ZRegSElem|32-bit element of SVE register #N|\n|z0.d[0], z0.d[1], ..., z0.d[15]|ZRegDElem|64-bit element of SVE register #0|\n|vN.d[0], vN.d[1], ..., vN.d[15]|ZRegDElem|64-bit element of SVE register #N|\n|z0.q[0], z0.q[1], ..., z0.q[15]|ZRegDElem|128-bit element of SVE register #0|\n|vN.q[0], vN.q[1], ..., vN.q[15]|ZRegDElem|128-bit element of SVE register #N|\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nZRegBElem hoge(1, 7, 8);\n\ndup(z0.b, z1.b[7]);  \u003c--- (1)\nadd(z0.b, hoge);     \u003c--- Output is same JIT code of (1)\n\n```\n\n### SVE register lists\n\nAs SVE register lists,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\nRegister index can be cyclic.\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|z0.b - z0.b|ZRegBList|SVE register list containing 8-bit elements x 64 x 1|\n|z0.b - z1.b|ZRegBList|SVE register list containing 8-bit elements x 64 x 2|\n|z0.b - z2.b|ZRegBList|SVE register list containing 8-bit elements x 64 x 3|\n|z0.b - z3.b|ZRegBList|SVE register list containing 8-bit elements x 64 x 4|\n|z31.b - z2.b|ZRegBList|SVE register list containing 8-bit elements x 64 x 4|\n|z0.h - z3.h|ZRegHList|SVE register list containing 16-bit elements x 32 x 4|\n|z0.s - z3.s|ZRegSList|SVE register list containing 32-bit elements x 16 x 4|\n|z0.d - z3.d|ZRegDList|SVE register list containing 64-bit elements x 8 x 4|\n|z0.q - z3.q|ZRegQList|SVE register list containing 128-bit elements x 4 x 4|\n\n```\nZRegBList dstList(z0.b, z3.b);\nZRegBList hoge(ZRegB(0) - ZRegB(3));\n\nld4((z0.b - z3.b), p0, ptr(x0)); \u003c--- (1)\nld4(dstList, p0, ptr(x0));       \u003c--- Output is same JIT code of (1)\nld4(hoge, p0, ptr(x0));          \u003c--- Output is same JIT code of (1)\n\n```\n\n### Element of SVE register lists\n\nAs elements of SVE register lists,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|(z0.b - z0.b)[0]|ZRegBElem|First 8-bit elements of one-SVE-register list|\n|(z0.b - z0.b)[N]|ZRegBElem|N-th 8-bit elements of one-SVE-register list|\n|(z0.b - z3.b)[N]|ZRegBElem|N-th 8-bit elements of four-SVE-register list|\n|(z0.h - z3.h)[N]|ZRegHElem|N-th 16-bit elements of four-SVE-register list|\n|(z0.s - z3.s)[N]|ZRegSElem|N-th 32-bit elements of four-SVE-register list|\n|(z0.d - z3.d)[N]|ZRegDElem|N-th 64-bit elements of four-SVE-register list|\n\nYou can also use your original instance as mnemonic functions argumetns analogous with the element of vector register lists.\n\n\n### Predicate registers\n\nAs predicate registers,\nthe following table shows example of mnemonic functions' arguments (\"Instance name\" column).\n\n|Instance name|C++ class name|Remarks|\n|----|----|----|\n|p0, p1, ..., p7|PReg|Predicate registers|\n|p0.b, p1.b, ..., p7.b|PRegB|Predicate registers for 8-bit elements|\n|p0.h, p1.h, ..., p7.h|PRegH|Predicate registers for 16-bit elements|\n|p0.s, p1.s, ..., p7.s|PRegS|Predicate registers for 32-bit elements|\n|p0.d, p1.d, ..., p7.d|PRegD|Predicate registers for 64-bit elements|\n\nThough Xbyak_aarch64 defines PRegB, PRegH, PRegS, PRegD classes,\nyou can use PReg class instances where mnemonic functions take predicate register operands.\nThe AArch64 instructin set has two predication types, \"merging\" and \"zeroing\" predicate.\nYou can use \"T_m\" or \"T_z\" to inform mnemonic functions which type you choses ((1), (2)).\n\nYou can ommit \"T_m\" and \"T_z\" for mnemonic functions whose correspond predicate instructions\ncan take either one. For example, \"CLS\" instruction in the AARch64 instruction set is only defined for merging predicate,\nboth (3) and (4) are OK.\n\nSome instructions are defined for both predicated and unpredicated.\nOutput JIT-ed code of (5) and (6) are deferent.\n\n\n```\nmov(z0.b, p0/T_m, 1);              \u003c--- (1), merging predicate\nmov(z0.b, p0/T_z, 1);              \u003c--- (2), zeroing predicate\n\ncls(z0.b, p0/T_m, z0.b);           \u003c--- (3)\ncls(z0.b, p0, z0.b);               \u003c--- (4), output is same JIT code of (3)\n\nadd(z0.b, p0/T_m, z1.b, z2.b);     \u003c--- (5), predicated add\nadd(z0.b, p0, z1.b, z2.b);         \u003c--- (6), output is same JIT code of (5)\nadd(z0.b, z1.b, z2.b);             \u003c--- (7), unpredicated add, output is NOT same JIT code of (5)\n```\n\nYou can also use your original instance as mnemonic functions argumetns.\nPlease refer constructor of \"C++ class name\" in Xbyak_aarch64 files.\n\n```\nPReg hoge(0);\n\nadd(z0.b, p0, z1.b, z2.b);         \u003c--- (8)\nadd(z0.b, PReg(0), z1.b, z2.b);    \u003c--- Output is same JIT code of (8)\nadd(z0.b, hoge, z1.b, z2.b);       \u003c--- Output is same JIT code of (8)\n\n```\n\n### Immediate values\n\nYou can use immediate values for arguments of mnemonic functions in the form that C++ syntax allows,\nsuch as, \"10\", \"-128\", \"0xFF\", \"1\u003c\u003c32\", \"3.5\", etc.\n\nPlease care for range of values.\nFor example, \"ADD (immediate)\" instruction can receive signed 12-bit value\nso that you have to ensure that the value passed to mnemonic function is inside the range.\nMnemonic functions of Xbyak_aarch64 checks immediate values at runtime,\nand throws exception if it detects range over.\n\n```\nvoid genAddFunc() {\n     int a = 1\u003c\u003c16;\n     add(x0, x0, a);    \u003c--- This mnemonic function throws exception at runtime.\n     ret();\n}\n```\n\nSome immediate values may not decided at coding time but runtime.\nYou should check the immediate values and handle them.\n\n```\nvoid gen_Summation_From_One_To_Parameter_Func(unsigned int N) {\n\n    if(N \u003c (1\u003c\u003c11)) {\n        for(int i=0; i\u003cN; i++) {\n            add(x0, x0, N);\n        }\n        ret();\n    } else {\n        printf(\"Invalid parameter N=%d\\n\", N);\n        printf(\"This function supports less than 2048.\\n\");\n    }\n}\n```\n\n#### Symbols\nSome instructions of the AArch64 instruction set are used with sybols such as **\"UXTW\", \"LSL\", \"SXTW\", \"SXTX\", \"MUL VL\"**, etc.\nThe menomic functions for those instructions can receive keywords of **\"UXTW\", \"LSL\", \"SXTW\", \"SXTX\", \"MUL_VL\"**, etc.\nPlease **\"grep**\" keywords, for example\n```\ngrep LSL sample/mnemonic_syntax/*\n```\n, to find usage of those menomic functions.\n\n\n#### Addressing\nThe AArch64 instruction set has various addressing modes such as \"No offset\", \"Post-index\", \"Pre-index\", \"Signed offset\", \"Unsigned offset\".\nPlease use \"ptr()\", \"pre_ptr()\", \"post_ptr()\" functions to specify which addressing mode you want to use.\nPlease \"grep\" the functions, for example\n```\ngrep -w ptr sample/mnemonic_syntax/*\n```\n, to find usage of these addressing functions.\n\n\n|Use example|corresponding assembler syntax|Remarks|\n|----|----|----|\n|ldr(x0, ptr(x1, x7))|ldr x0, [x1, x7]|Register offset|\n|str(w0, ptr(x7, w8, UXTW, 2))|str w0, [x7, w8, UXTW 2]|Register offset with shift amount|\n|ldr(w0, post_ptr(x5, -16))|ldr w0, [x5], -16|Post-index|\n|ldrb(w16, pre_ptr(x5, 127))|ldrb w16, [x5, 127]!|Pre-index|\n\n\n## Label\n\nYou can use \"Label\" to direct where branch instruction jump to.\nThe following example shows how to use \"Label\".\n\n```\nLabel L1;           // (1), instance of Label class\n\nmov(w4, w0);\nmov(w3, 0);\nmov(w0, 0);\nL(L1);              // (2), \"L\" function registers JIT code address of this position to label L1.\nadd(w0, w0, w4);\nadd(w3, w3, 1);\ncmp(w2, w3);\nccmp(w1, w3, 4, NE);\nbgt(L1);            // (3), set destination of branch instruction to the address stored in L1.\n```\n\n1. Prepare Label class instance.\n1. Call the L function to register destination address to the instance.\n1. Pass the instance to mnemonic functions correspond to branch instructions.\n\nYou can copy the address stored in \"Label\" instance by using `assignL` function.\n\n```\nLabel L1,L2,L3;\n....\nL(L1);               // JIT code address of this position is stored to L1.\n....\nL(L2);               // JIT code address of this position is stored to L1.\n....\nif (flag) {\nassignL(L3,L1);      // The address stored in L1 is copied to L3.\n} else {\nassignL(L3,L2);      // The address stored in L1 is copied to L3.\n}\nb(L3);               // If flag == true, branch destination is L1, otherwise L2.\n```\n\n\n\n## Code size\nThe default max size of JIT-ed code is 4096 bytes.\nSpecify the size in constructor of `CodeGenerator()` if necessary.\n\n```\nclass Quantize : public Xbyak_aarch64::CodeGenerator {\npublic:\n  Quantize()\n    : CodeGenerator(8192)\n  {\n  }\n  ...\n};\n```\n\n## User allocated memory\n\nYou can make JIT-ed code on prepared memory.\n\nCall `setProtectModeRE` yourself to change memory mode if using the prepared memory.\n\n```\nuint8_t alignas(4096) buf[8192]; // C++11 or later\n\nstruct Code : Xbyak_aarch64::CodeGenerator {\n    Code() : Xbyak_aarch64::CodeGenerator(sizeof(buf), buf)\n    {\n        mov(rax, 123);\n        ret();\n    }\n};\n\nint main()\n{\n    Code c;\n    c.setProtectModeRE(); // set memory to Read/Exec\n    printf(\"%d\\n\", c.getCode\u003cint(*)()\u003e()());\n}\n```\n\n**Note**: See [sample/test0.cpp](sample/test0.cpp).\n\n### AutoGrow\n\nIf `AutoGrow` is specified in a constructor of `CodeGenerator`,\nthe memory region for JIT-ed code is automatically extended if needed.\n\nCall `ready()` or `readyRE()` before calling `getCode()` to fix jump address.\n```\nstruct Code : Xbyak_aarch64::CodeGenerator {\n  Code()\n    : Xbyak_aarch64::CodeGenerator(\u003cdefault memory size\u003e, Xbyak_aarch64::AutoGrow)\n  {\n     ...\n  }\n};\nCode c;\n// generate code for jit\nc.ready(); // mode = Read/Write/Exec\n```\n\n**Note**:\n* Don't use the address returned by `getCurr()` before calling `ready()` because it may be invalid address.\n\n### Read/Exec mode\nXbyak_aarch64 set Read/Write/Exec mode to memory to run JIT-ed code.\nIf you want to use Read/Exec mode for security, then specify `DontSetProtectRWE` for `CodeGenerator` and\ncall `setProtectModeRE()` after generating JIT-ed code.\n\n```\nstruct Code : Xbyak_aarch64::CodeGenerator {\n    Code()\n        : Xbyak_aarch64::CodeGenerator(4096, Xbyak_aarch64::DontSetProtectRWE)\n    {\n        mov(eax, 123);\n        ret();\n    }\n};\n\nCode c;\nc.setProtectModeRE();\n```\n\n\nCall `readyRE()` instead of `ready()` when using `AutoGrow` mode.\n\n## How to pass arguments to JIT generated function\nTo be written...\n\n## Macro\nTo be written...\n\n\n## Sample\nTo be written...\n\n* [add.cpp](sample/add.cpp) ; tiny sample\n* [label.cpp](sample/label.cpp) ; label sample\n\n## License\n\nCopyright FUJITSU LIMITED 2019-2020\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n    http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\n## Reference\n- Chapter C6:A64 Base Instruction Descriptions and C7:A64 Advanced SIMD and Floating-point Instruction Descriptions of \"ARM(R) Architecture Reference Manual ARMv8, for ARMv8-A architecture profile\", ARM DDI 0487D.b (ID042519)\".\n- \"ARM(R) Architecture Reference Manual Supplement, The Scalable Vector Extension (SVE), for ARMv8-A\", ARM DDI0584.\n- \"Procedure Call Standard for the ARM 64-bit Architecture (AArch64)\",  ARM IHI 0055B\".\n- [Xbyak_aarch64; Just-In-Time Assembler for Armv8-A and Scalable Vector Extension](https://connect.linaro.org/resources/lvc21/lvc21-203/)\n- [Development of Deep Learning Library for AArch64 CPU](https://connect.linaro.org/resources/lvc21f/lvc21f-212/)\n- [A Binary Translator to Accelerate Development of Deep Learning Processing Library for AArch64 CPU](https://search.ieice.org/bin/pdf_advpub.php?category=C\u0026lang=E\u0026fname=2021LHP0001\u0026abst=)\n\n\n\n## Notice\n\n* Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.\n* Intel is a registered trademark of Intel Corporation (or its subsidiaries) in the US and/or elsewhere.\n\n\n\n## Acknowledgement\n\nWe are grateful to MITSUNARI-san (Cybozu Labs, Inc.) for release Xbyak as an open source software and his advice for development of Xbyak_aarch64.\n\n## History\n\n|Date|Version|Remarks|\n|----|----|----|\n|December 9, 2019|0.9.0|First public release version.|\n\n\n## Copyright\n\nCopyright FUJITSU LIMITED 2019-2020\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffujitsu%2Fxbyak_aarch64","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffujitsu%2Fxbyak_aarch64","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffujitsu%2Fxbyak_aarch64/lists"}