{"id":20041474,"url":"https://github.com/furkankayar/deuarc","last_synced_at":"2026-03-19T13:11:54.420Z","repository":{"id":131031185,"uuid":"180419180","full_name":"furkankayar/DEUARC","owner":"furkankayar","description":"DEUARC RISC computer design in Quartus II 13.0","archived":false,"fork":false,"pushed_at":"2020-02-23T14:15:13.000Z","size":7860,"stargazers_count":2,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-02T06:49:28.451Z","etag":null,"topics":["processor-architecture","quartus2","risc"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/furkankayar.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-04-09T17:40:28.000Z","updated_at":"2021-10-14T06:24:28.000Z","dependencies_parsed_at":"2023-04-13T15:23:01.591Z","dependency_job_id":null,"html_url":"https://github.com/furkankayar/DEUARC","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/furkankayar/DEUARC","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/furkankayar%2FDEUARC","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/furkankayar%2FDEUARC/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/furkankayar%2FDEUARC/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/furkankayar%2FDEUARC/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/furkankayar","download_url":"https://codeload.github.com/furkankayar/DEUARC/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/furkankayar%2FDEUARC/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30214608,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-07T12:15:00.571Z","status":"ssl_error","status_checked_at":"2026-03-07T12:15:00.217Z","response_time":53,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["processor-architecture","quartus2","risc"],"created_at":"2024-11-13T10:46:43.066Z","updated_at":"2026-03-07T13:01:37.438Z","avatar_url":"https://github.com/furkankayar.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003ch1\u003eRISC Computer design in Quartus II 13.0\u003ch1\u003e\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"/Circuit.png\" width=\"1607\"/\u003e\n  \u003cimg src=\"/Control_Functions_and_Microoperations.png\" width=\"604\"/\u003e\n\u003c/p\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffurkankayar%2Fdeuarc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Ffurkankayar%2Fdeuarc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Ffurkankayar%2Fdeuarc/lists"}