{"id":46600556,"url":"https://github.com/google/aarch64-rt","last_synced_at":"2026-03-07T16:03:11.080Z","repository":{"id":281577334,"uuid":"928973681","full_name":"google/aarch64-rt","owner":"google","description":"Startup code and exception vector for bare-metal Rust on aarch64 Cortex-A processors.","archived":false,"fork":false,"pushed_at":"2026-02-23T00:20:07.000Z","size":138,"stargazers_count":25,"open_issues_count":1,"forks_count":9,"subscribers_count":2,"default_branch":"main","last_synced_at":"2026-03-03T09:17:34.212Z","etag":null,"topics":["aarch64","arm","cortex-a","no-std","rust","rust-crate"],"latest_commit_sha":null,"homepage":"","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/google.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":"AUTHORS","dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-02-07T15:23:16.000Z","updated_at":"2026-03-02T13:40:04.000Z","dependencies_parsed_at":"2025-03-10T03:05:25.504Z","dependency_job_id":"68b1d087-d7a4-4980-874c-ed53833f6d7d","html_url":"https://github.com/google/aarch64-rt","commit_stats":null,"previous_names":["google/aarch64-rt"],"tags_count":12,"template":false,"template_full_name":null,"purl":"pkg:github/google/aarch64-rt","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Faarch64-rt","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Faarch64-rt/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Faarch64-rt/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Faarch64-rt/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/google","download_url":"https://codeload.github.com/google/aarch64-rt/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Faarch64-rt/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30079646,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-04T11:57:42.557Z","status":"ssl_error","status_checked_at":"2026-03-04T11:56:10.793Z","response_time":59,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["aarch64","arm","cortex-a","no-std","rust","rust-crate"],"created_at":"2026-03-07T16:03:10.514Z","updated_at":"2026-03-07T16:03:11.073Z","avatar_url":"https://github.com/google.png","language":"Rust","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Startup code for bare-metal aarch64\n\n[![crates.io page](https://img.shields.io/crates/v/aarch64-rt.svg)](https://crates.io/crates/aarch64-rt)\n[![docs.rs page](https://docs.rs/aarch64-rt/badge.svg)](https://docs.rs/aarch64-rt)\n\nThis crate provides entry point and exception handling for bare-metal Rust binaries on aarch64\nCortex-A processors.\n\nThis is not an officially supported Google product.\n\n## Usage\n\nUse the `entry!` macro to mark your main function:\n\n```rust\nuse aarch64_rt::entry;\n\nentry!(main);\nfn main(arg0: u64, arg1: u64, arg2: u64, arg3: u64) -\u003e ! {\n    // ...\n}\n```\n\n`arg0` through `arg3` will contain the initial values of registers `x0`–`x3`. These are often used\nto pass arguments from the previous-stage bootloader, such as the address of the device tree.\n\nYou'll need to provide the image origin (which will be the entry point address) and maximum size in a linker script, e.g.:\n\n```ld\nMEMORY\n{\n    image : ORIGIN = 0x40080000, LENGTH = 2M\n}\n```\n\nYou'll need to tell Rust to use both this and the `aarch64-rt` linker script in your `build.rs`.\nAssuming your linker script is called `memory.ld`:\n\n```rust\nfn main() {\n    println!(\"cargo:rustc-link-arg=-Timage.ld\");\n    println!(\"cargo:rustc-link-arg=-Tmemory.ld\");\n    println!(\"cargo:rerun-if-changed=memory.ld\");\n}\n```\n\n## Features\n\n`exceptions`, `initial-pagetable` and `psci` are enabled by default.\n\n### `el1`\n\nIf the `exceptions` feature is also enabled then uses `vbar_el1` for the exception vector. If\n`initial-pagetable` is also enabled then uses `ttbr0_el1` for the page table, and other EL1 MMU\nconfiguration registers.\n\n### `el2`\n\nIf the `exceptions` feature is also enabled then uses `vbar_el2` for the exception vector. If\n`initial-pagetable` is also enabled then uses `ttbr0_el2` for the page table, and other EL2 MMU\nconfiguration registers.\n\n### `el3`\n\nIf the `exceptions` feature is also enabled then uses `vbar_el3` for the exception vector. If\n`initial-pagetable` is also enabled then uses `ttbr0_el3` for the page table, and other EL3 MMU\nconfiguration registers.\n\n### `exceptions`\n\nProvides an exception vector table, and sets it in the appropriate `vbar` system register for the\nselected exception level. You must provide handlers for each exception by implementing the\n`ExceptionHandlers` trait and then calling the `exception_handlers!` macro. All methods on\n`ExceptionHandlers` have a default implementation which simply panics, so the simplest\nimplementation looks like this:\n\n```rust\nexception_handlers!(Exceptions);\n\nstruct Exceptions;\n\nimpl ExceptionHandlers for Exceptions {}\n```\n\n### `initial-pagetable`\n\nSets an initial pagetable in the appropriate TTBR and enables the MMU and cache before running any\nRust code or writing to any memory.\n\nThis is especially important if running at EL1 in a VM, as accessing memory with the cache disabled\nwhile the hypervisor or host has cacheable aliases to the same memory can lead to cache coherency\nissues. Even if the host doesn't explicitly access the memory, speculative accesses can lead to\ncache fills.\n\nThis may be combined with one of the `elX` features to set up the page table for that exception\nlevel. If not, the exception level will be checked at runtime and the corresponding system registers\nused.\n\n### `psci`\n\nAdds the `start_core` function to start another CPU core via a PSCI `CPU_ON` call. This adds a\ndependency on the `smccc` crate.\n\n## License\n\nLicensed under either of\n\n- Apache License, Version 2.0\n  ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0)\n- MIT license\n  ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)\n\nat your option.\n\n## Contributing\n\nIf you want to contribute to the project, see details of\n[how we accept contributions](CONTRIBUTING.md).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fgoogle%2Faarch64-rt","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fgoogle%2Faarch64-rt","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fgoogle%2Faarch64-rt/lists"}