{"id":13772854,"url":"https://github.com/google/bigspicy","last_synced_at":"2025-05-11T05:33:49.016Z","repository":{"id":38818484,"uuid":"490461583","full_name":"google/bigspicy","owner":"google","description":null,"archived":true,"fork":false,"pushed_at":"2023-04-10T00:15:59.000Z","size":232,"stargazers_count":41,"open_issues_count":8,"forks_count":9,"subscribers_count":7,"default_branch":"main","last_synced_at":"2025-04-19T22:27:10.021Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/google.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"docs/contributing.md","funding":null,"license":"LICENSE","code_of_conduct":"docs/code-of-conduct.md","threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2022-05-09T22:22:27.000Z","updated_at":"2025-04-14T08:43:12.000Z","dependencies_parsed_at":"2024-01-15T04:08:11.049Z","dependency_job_id":"df93db4b-0a44-493b-be38-a60a51740984","html_url":"https://github.com/google/bigspicy","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Fbigspicy","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Fbigspicy/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Fbigspicy/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/google%2Fbigspicy/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/google","download_url":"https://codeload.github.com/google/bigspicy/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":253523689,"owners_count":21921815,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-03T17:01:08.540Z","updated_at":"2025-05-11T05:33:48.685Z","avatar_url":"https://github.com/google.png","language":"Python","funding_links":[],"categories":["Circuit Compilers"],"sub_categories":[],"readme":"# bigspicy\n\n`bigspicy` is a tool for merging circuit descriptions (netlists), generating\nSpice decks modeling those circuits, generating Spice tests to measure those\nmodels, and analyzing the results of running Spice on those tests.\n\n`bigspicy` allows you to combine structural Verilog from a PDK, Spice models of\nstandard cells, a structural Verilog model of some circuit implemented in that\nPDK, and parasitics extracted into SPEF format. You can then reason about the\nelectrical structure of the design however you want.\n\n`bigspicy` generates Spice decks in `Xyce` format, though this can (and should)\nbe extended to other Spice dialects. (That is why we recommend setting up\n`Xyce` below.) \n\n## Prerequisites\n\nYou need:\n- The protocol buffer compiler `protoc` \n- Icarus Verilog\n- Xyce\n  - Note this one is special, and takes some more care. \n- python3 (see `requirements.txt`)\n  - pyverilog\n  - numpy\n  - matplotlib\n  - protobuf\n\nOn debian-family Linuxes, several of the system-installed dependencies can be\ninstalled with  \n\n```\nsudo apt install -y protobuf-compiler iverilog\n```\n\nGiven a `python` installation and environment, all other Python dependencies can\nbe installed with  \n\n```\npip install -e \".[dev]\"\npip install -r requirements.txt\n```\n\n### Set up Xyce\n\nInstall the 'Serial' or 'Parallel' versions of Xyce. Follow the\n[Xyce Building Guide](https://xyce.sandia.gov/documentation/BuildingGuide.html).\n\n### Set up XDM\n\n[XDM](https://github.com/Xyce/XDM) is needed to prepare Spice netlists generated\nfor common proprietary Spice engines for use with `Xyce`. It is only needed to\nprepare the input libraries used by `bigspicy`, and only once for each corner in\nthe PDK.\n\nFollow the XDM [installation instructions](https://github.com/Xyce/XDM) on their\nGitHub clone. If existing XDM-translated libraries are available, you can skip\nthis step.\n\n#### XDM 2.5.0/Debian 11.4 build cheat-sheet\n\n```\nsudo apt install libboost-dev libboost-python-dev\nsudo pip3 install pyinstaller  # 'sudo' needed to be install in site packages dir\nwget https://github.com/Xyce/XDM/archive/refs/tags/Release-2.5.0.tar.gz\ntar xf XDM-Release-2.5.0.tar.gz\ncd XDM-Release-2.5.0/\nmkdir build \u0026\u0026 cd build\ncmake -DBOOST_ROOT=/usr/include/boost ../\nmake -j $(nproc)\nsudo make install\n```\n\n## Compile protos and prepare PDK models\n\n### Generating SPICE library files\n\nSpice files fed to `bigspicy` should be in `Xyce` format because `bigspicy` does\nminimal internal processing of the files and will include them almost verbatim.\nThese files are in turn read directly into Xyce.\nThat means that any PDK Spice files you receive should be converted to `Xyce`'s\nspice dialect. The `xdm_bdl` tool (XDM) can usually do this for you, though\nin some cases you will need to interfere by hand :(\n\n#### e.g. Convert ASAP7 models using `xdm_bdl`\n\nFor example, for the `TT` corner and `RVT` ASAP7 cells:\n```\nxdm_bdl -s hspice ${HOME}/src/asap7PDK_r1p7/models/hspice/7nm_TT.pm -d lib\nxdm_bdl -s hspice ${HOME}/src/asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_R.sp -d lib\n```\n\nThese can then be included as Spice headers (blackboxes) or full Spice modules\nusing the `--spice_header`/`--spice` arguments, e.g:\n\n```\n[...]\n    --spice_header lib/7nm_TT.pm \\\n    --spice_header lib/asap7sc7p5t_27_R.sp \\\n[...]\n```\n\n### Compile protobufs\n\n```\ngit submodule update --init   # Make sure we pull from Vlsir/schema-proto the\n                              # first time.\nprotoc --proto_path vlsir vlsir/*.proto vlsir/*/*.proto --python_out=.\nprotoc proto/*.proto --python_out=.\n```\n\n## Usage\n\n\n### Merge SPEF, Verilog and Spice information into Circuit protobuf\n\nIn addition to some circuit definition, in order to generate a Spice deck the\norder of ports for each instantiated module are also required. When relying on\nPDK cells, that usually means providing the PDK spice models as a header.\n\nIn the example below, `lib/sky130_fd_sc_hd.spice` is copied from\n`${PDK_ROOT}/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice`\nas it is produced by\n[`open_pdks`](https://github.com/RTimothyEdwards/open_pdks).\n\n```\n./bigspicy.py \\\n    --import \\\n    --verilog example_inputs/fp_multiplier/fp_multiplier.synth.v \\\n    --spef /path/to/fp_multiplier/fp_multiplier.spef \\\n    --spice_header lib/sky130_fd_sc_hd.spice \\\n    --top fp_multiplier \\\n    --save final.pb \\\n    --working_dir /tmp/bigspicy\n```\n\n### Generate whole-module Spice model\n\n```\n./bigspicy.py \\\n    --load /tmp/bigspicy/final.pb \\\n    --spice_header lib/sky130_fd_sc_hd.spice \\\n    --top fp_multiplier \\\n    --dump_spice fp_multiplier.sp\n```\n\n### Generate whole-module Spice model with transistors\n\nRequires models for the PDK standard cells (included as full-fat netlists with\n`--spice`) and also black-box models for the transistors (included with\n`--spice_header`). Then pass the `--flatten_spice` argument.\n\nIf you had started with a gate-level netlist for an ASAP7 design, for example,\nyou could do this:\n\n```\n./bigspicy.py \\\n    --load /tmp/bigspicy/final.pb \\\n    --spice_header lib/7nm_TT.pm \\\n    --spice lib/asap7sc7p5t_27_R.sp \\\n    --top fp_multiplier_asap7 \\\n    --flatten_spice \\\n    --dump_spice fp_multiplier_asap7.sp\n```\n\n### Generate tests to measure input capacitance\n\n```\n./bigspicy.py \\\n    --load /tmp/bigspicy/final.pb \\\n    --spice_header lib/7nm_TT.pm \\\n    --spice_header lib/asap7sc7p5t_27_R.sp \\\n    --top fp_multiplier_asap7 \\\n    --working_dir /tmp/bigspicy \\\n    --generate_input_capacitance_tests\n```\n\nThis will generate all necessary test files in `/tmp/bigspicy`. It will also\ngenerate a test manifest, `test_manifest.pb`, and an analysis file\n`circuit_analysis.pb`, which you must specify as paths to subsequent analysis\nsteps.\n\n#### Run Xyce to perform tests\n\n```\ncd /tmp/bigspicy\nfor test in *.linearZ.sp *.transient_*.sp; do\n  ~/XyceInstall/Serial/bin/Xyce \"${test}\" \u0026\ndone\n```\n\n### Generate wire and whole-module tests\n\n```\n./bigspicy.py \\\n    --load /tmp/bigspicy/final.pb \\\n    --spice lib/7nm_TT.pm \\\n    --spice lib/asap7sc7p5t_27_R.sp \\\n    --top fp_multiplier_asap7 \\\n    --working_dir /tmp/bigspicy \\\n    --generate_module_tests \\\n    --test_manifest /tmp/bigspicy/test_manifest.pb \\\n    --test_analysis /tmp/bigspicy/analysis.pb\n```\n\n#### Include results of external module measurements\n\n```\n./bigspicy.py \\\n    --load /tmp/bigspicy/final.pb \\\n    --spice lib/7nm_TT.pm \\\n    --spice lib/asap7sc7p5t_27_R.sp \\\n    --top fp_multiplier_asap7 \\\n    --working_dir /tmp/bigspicy \\\n    --generate_module_tests \\\n    --test_manifest /tmp/bigspicy/test_manifest.pb \\\n    --test_analysis /tmp/bigspicy/analysis.pb \\\n    --analyze_input_capacitance_tests\n```\n\n#### Run Xyce to perform tests\n\n```\ncd /tmp/bigspicy\nfor test in *.linearY.sp *.transient.sp; do\n  ~/XyceInstall/Serial/bin/Xyce \"${test}\" \u0026\ndone\n```\n\n### Perform analysis on wire and whole-module tests\n\n```\n./bigspicy.py \\\n    --load /tmp/bigspicy/final.pb \\\n    --spice lib/7nm_TT.pm \\\n    --spice lib/asap7sc7p5t_27_R.sp \\\n    --top fp_multiplier_asap7 \\\n    --working_dir /tmp/bigspicy \\\n    --test_manifest /tmp/bigspicy/test_manifest.pb \\\n    --test_analysis /tmp/bigspicy/analysis.pb \\\n    --analyze_module_tests \\\n    --input_caps_csv=input_caps.csv \\\n    --delays_csv=delays.csv\n```\n\n### Import all Skywater 130 `sky130_fd_sc_hd` standard cells into circuit proto\n\n```\n./bigspicy.py \\\n    --import \\\n    --spice ${PDK_ROOT}/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice\n    --save sky130hd.pb\n    --working_dir /tmp/bigspicy\n```\n\n### Import all Skywater 130 primitives too\n\nCaution! Globbing every spice file as in this example is not a good idea. You\nwill likely end up with multiple definitions for the same circuit. But you can\ndo it if you want.\n```\n./bigspicy.py \\\n    --import \\\n    --spice ${PDK_ROOT}/share/pdk/sky130A/libs.ref/sky130_fd_pr/spice/sky130_fd_pr__\\* \\\n    --spice ${PDK_ROOT}/share/pdk/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice \\\n    --save sky130hd.pb \\\n    --working_dir /tmp/bigspicy\n```\n\nLikely:\n```\nwarning: multiple definitions for subckt sky130_fd_pr__rf_nfet_01v8_bM04W3p00, overwriting previous\n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fgoogle%2Fbigspicy","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fgoogle%2Fbigspicy","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fgoogle%2Fbigspicy/lists"}