{"id":17648065,"url":"https://github.com/gpanders/fpga-design-template","last_synced_at":"2026-01-11T01:10:46.634Z","repository":{"id":102162281,"uuid":"169419714","full_name":"gpanders/fpga-design-template","owner":"gpanders","description":"Project template for Xilinx-based FPGA designs","archived":false,"fork":false,"pushed_at":"2019-08-07T20:22:04.000Z","size":24,"stargazers_count":3,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-02-05T09:52:00.416Z","etag":null,"topics":["fpga","template","xilinx"],"latest_commit_sha":null,"homepage":"","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/gpanders.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-02-06T14:35:13.000Z","updated_at":"2024-09-23T16:31:53.000Z","dependencies_parsed_at":"2023-07-11T17:16:45.083Z","dependency_job_id":null,"html_url":"https://github.com/gpanders/fpga-design-template","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/gpanders%2Ffpga-design-template","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/gpanders%2Ffpga-design-template/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/gpanders%2Ffpga-design-template/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/gpanders%2Ffpga-design-template/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/gpanders","download_url":"https://codeload.github.com/gpanders/fpga-design-template/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246290583,"owners_count":20753724,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","template","xilinx"],"created_at":"2024-10-23T11:16:10.833Z","updated_at":"2026-01-11T01:10:46.593Z","avatar_url":"https://github.com/gpanders.png","language":"Tcl","funding_links":[],"categories":[],"sub_categories":[],"readme":"# FPGA Design Template\n\nFPGA project design template for use with Xilinx Vivado.\n\n## Introduction\n\nThis project serves as a template for Xilinx based FPGA projects. Currently,\nonly Linux is supported.\n\nThe motivation of this project was to get away from being constrained by\nVivado's clunky GUI. While the Vivado GUI is often useful and sometimes\nnecessary, most of the time it is not, and there are significant speed and\nproductivity improvements to be had by moving to a scripted command-line flow.\n\nOrganizing the project as a software project allows us to leverage many of the\ntools that software developers have been using for years, such as version\ncontrol, release tagging, and automated testing.\n\n## Design Flow\n\nDefine your project settings such as project name, part, top level module, and\nconstraints files in `settings.conf`.\n\nThe `Makefile` is the entry point for executing all tasks. Running `make help`\nwill provide a list of all available targets. Each target in turn sources a Tcl\nscript (found in the `scripts/tcl` directory) which uses the settings specified\nin `settings.conf` to build the design.\n\nThe Tcl scripts look for all source files under the `src` directory.  HDL design\nfiles should go under `src/hdl/`, block designs should go in\n`src/bd/\u003cbd_name\u003e/`, and constraints under `src/xdc/`.\n\n**Constraints file are not read as globs and must be explicitly specified in the\nsettings.conf file**. This is because it is Xilinx's recommended best practice\nto separate synthesis constraints from implementation constraints (see [Vivado\nUser Guide: Using Constraints][ug903]).  All other source files are read as\nglobs, meaning if the file exists under `src/` it will be read.\n\nOnce all of your source design files, constraints, and IP are ready, you can\ncreate a bitstream using\n\n    make bitstream\n\nAnd you can program the device using\n\n    make program_device\n\nThe Makefile also provides other targets for design analysis. See `make help`\nfor all options.\n\n## Creating a Project\n\nThe make-based work flow is designed to work in non-project flow. Non-project\nflow has many benefits, not the least of which is speed; however, there are some\nthings that are either much easier to do in project mode or that _must_ be done\nin project mode. For that purpose, you can easily create a project from your\ndesign sources using\n\n    make project\n\nThis will create a Vivado project under the `proj` directory.\n\n## Managing IP\n\nFollowing Xilinx's recommendations, this design utilizes a managed IP project to\ngenerate and manage all project IP. To create IP for use in your design, open\nthe managed IP project in Vivado and create and configure your IP from the IP\ncatalog. Be sure that your IP is created in the `ip/` directory (this is the\ndefault). The Tcl build scripts look for IP files (either `.xci` or `.xcix`)\nunderneath this directory.\n\nSee chapter 3, \"Using Manage IP Projects\" of [Vivado User Guide: Designing With\nIP][ug896] for more information.\n\n## Simulating and Testing\n\nThe `sim` directory contains files for simulation. Each module to be simulated\nshould exist in its own directory, and each directory should contain a `.prj`\nfile enumerating the source files used in that module and a top-level HDL\ntestbench file. The test bench should should be self-checking and should fail\n(i.e. using an assert statement) if the simulation does not match expected\noutput.\n\nExample:\n\n    sim\n    └── my_module\n        ├── my_module.prj\n        ├── my_module_tb.vhd\n        ├── golden_data.dat\n        └── input_data.dat\n\n[ug903]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug903-vivado-using-constraints.pdf\n[ug896]: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug896-vivado-ip.pdf\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fgpanders%2Ffpga-design-template","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fgpanders%2Ffpga-design-template","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fgpanders%2Ffpga-design-template/lists"}