{"id":20477347,"url":"https://github.com/harbaum/fdc1772-verilator","last_synced_at":"2026-03-06T08:32:09.884Z","repository":{"id":89283522,"uuid":"197758357","full_name":"harbaum/fdc1772-verilator","owner":"harbaum","description":"Verilator simulation for fdc1772 verilog implementation for PlusToo","archived":false,"fork":false,"pushed_at":"2019-08-19T18:26:38.000Z","size":1531,"stargazers_count":0,"open_issues_count":0,"forks_count":1,"subscribers_count":0,"default_branch":"master","last_synced_at":"2025-10-11T00:59:25.269Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/harbaum.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-07-19T11:05:44.000Z","updated_at":"2020-08-08T23:42:25.000Z","dependencies_parsed_at":"2023-04-11T04:47:26.764Z","dependency_job_id":null,"html_url":"https://github.com/harbaum/fdc1772-verilator","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/harbaum/fdc1772-verilator","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/harbaum%2Ffdc1772-verilator","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/harbaum%2Ffdc1772-verilator/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/harbaum%2Ffdc1772-verilator/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/harbaum%2Ffdc1772-verilator/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/harbaum","download_url":"https://codeload.github.com/harbaum/fdc1772-verilator/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/harbaum%2Ffdc1772-verilator/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30167962,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-06T07:56:45.623Z","status":"ssl_error","status_checked_at":"2026-03-06T07:55:55.621Z","response_time":250,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.6:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-15T15:27:40.385Z","updated_at":"2026-03-06T08:32:09.837Z","avatar_url":"https://github.com/harbaum.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# fdc1772 verilator simulation\n\nThis is a verilator environment written to test the floppy and fdc\nimplementation for the Archimedes FPGA \"Archie\" core.\n\nIt includes a testbench for the fdc incl. a floppy model. This\ncan be run by entering ```make```:\n\n```\nobj_dir/Vfdc1772\n[0.000] \"motor on\" at 300.000 RPM\n[0.000] Full RPM reached 0.000ms after motor on\n[0.000] Floppy becomes ready\n[0.000] Floppy motor timeout 5\nFORCED_INTERRUPT(0)\n[0.001] New command d0\nFORCED_INTERRUPT done\nREAD_ADDRESS 0\n[0.012] fdc becomes busy\n@28042us data: 00\n@32us data: 00\n@32us data: 01\n@32us data: 03\n@32us data: a5\n@32us data: 5a\n[0.040] IRQ raised\n[0.040] fdc becomes not busy. command done\n[0.040] Floppy motor timeout 9\n[0.040] IRQ cleared\nREAD_ADDRESS done, status = 80\nREAD_SECTOR\n[0.040] New command 88\n[0.040] fdc becomes busy\nDIO: READ SECTOR with empty fifo, starting 1k data\n@79804us data(0): 00\n@32us data(1023): ff\n[0.153] IRQ raised\n[0.153] fdc becomes not busy. command done\n[0.153] IRQ cleared\nREAD_SECTOR done, status = 80\nREAD_SECTOR\n[0.153] New command 88\n[0.153] fdc becomes busy\nDIO: READ SECTOR with empty fifo, starting 1k data\n@7228us data(0): 00\n@32us data(1023): ff\n[0.193] IRQ raised\n[0.193] fdc becomes not busy. command done\n[0.193] IRQ cleared\nREAD_SECTOR done, status = 80\n[0.193] done\n```\n\nit also contains a setup to test the floppy model itself by typing\n```make -f floppy.mk```:\n\n```\nobj_dir/Vfloppy\nmotor on at 0.000 RPM\nIndex pulse len = 5.000ms\nFull RPM reached 500.000ms after motor on\nRPM = 295.875\nIndex pulse len = 5.000ms\nRPM = 300.000\nIndex pulse len = 5.000ms\n```\n\nBoth simulations write .vcd files for further inspection using e.g.\ngtkwave.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fharbaum%2Ffdc1772-verilator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fharbaum%2Ffdc1772-verilator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fharbaum%2Ffdc1772-verilator/lists"}