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Which is a file at the top directory of every bazel\nrepo:\n\n```starlark\nload(\"@bazel_tools//tools/build_defs/repo:http.bzl\", \"http_archive\")\nload(\"@bazel_tools//tools/build_defs/repo:utils.bzl\", \"maybe\")\n\n# You don't need these variables, but are useful for configurability.\n# Feel free to hardcode these values in the maybe http_archive below.\nrules_hdl_git_hash = \"{LATEST_HASH}\"\nrules_hdl_git_sha256 = \"{LATEST_SHA}\"\n\nmaybe(\n    http_archive,\n    name = \"rules_hdl\",\n    sha256 = rules_hdl_git_sha256,\n    strip_prefix = \"bazel_rules_hdl-%s\" % rules_hdl_git_hash,\n    urls = [\n        \"https://github.com/hdl/bazel_rules_hdl/archive/%s.tar.gz\" % rules_hdl_git_hash,\n    ],\n)\n\nload(\"@rules_hdl//dependency_support:dependency_support.bzl\", rules_hdl_dependency_support = \"dependency_support\")\nrules_hdl_dependency_support()\n\nload(\"@rules_hdl//:init.bzl\", rules_hdl_init = \"init\")\nrules_hdl_init()\n```\n\n## Usage\n\nSee the following build file to synthesize a final ASIC design for a given piece\nof RTL written in verilog.\n\nThis file is called `counter.v`. It is a 128 bit counter incremented on every\npositive edge of a clock signial.\n\n```verilog\nmodule counter(\n  input wire clk,\n  input wire reset,\n  output [127:0] out,\n);\n  reg [127:0] counter_tmp;\n  always @ (posedge clk or posedge reset) begin\n    if (reset) begin\n      counter_tmp \u003c= 0;\n    end else begin\n      counter_tmp \u003c= counter_tmp + 1;\n    end\n  end\n\n  assign out = counter_tmp;\n\nendmodule\n\n```\n\nThe default PDK used is the Sky130 High Density standard cells.\n\nThis is the `BUILD` file. Every thing in bazel needs a rule description of what\nto build. The rules use yosys and OpenROAD to place and route your design.\n\n```python\nload(\"@rules_hdl//synthesis:defs.bzl\", \"synthesize_rtl\")\nload(\"@rules_hdl//place_and_route:build_defs.bzl\", \"place_and_route\")\nload(\"@rules_hdl//verilog:defs.bzl\", \"verilog_library\")\n\nplace_and_route(\n    name = \"counter_place_and_route\",\n    clock_period = \"10\",\n    core_padding_microns = 20,\n    die_height_microns = 200,\n    die_width_microns = 200,\n    placement_density = \"0.7\",\n    synthesized_rtl = \":verilog_counter_synth\",\n)\n\nsynthesize_rtl(\n    name = \"verilog_counter_synth\",\n    top_module = \"counter\",\n    deps = [\n        \":verilog_counter\",\n    ],\n)\n\nverilog_library(\n    name = \"verilog_counter\",\n    srcs = [\n        \"counter.v\",\n    ],\n)\n```\n\nAt this point you should have the following three files at the top of your bazel\nworkspace.\n\n```\nBUILD\ncounter.v\nWORKSPACE\n```\n\nWhen you run `bazel build //:counter_place_and_route`. It will output log files\nand a def file that represents the fully placed and routed design.\n\n# Project Vision\n`hdl/bazel_rules_hdl` is a project that is designed to be a one stop shop for doing hardware dev with bazel.\n\nThrough iteration we hope to eventually become an official bazel ruleset for doing HDL development.\n\nSo that includes;\n\n  * Supporting designs targeting FPGAs and ASIC.\n  * Supporting software targeted to run on this custom hardware.\n  * Supporting testing via simulation, formal verification, emulation and others.\n\nHaving rules that can take RTL and be chained to emit GDSII (Sky130/FOSS-PDKs), but that can also be used to target FPGAs and soft CPUs. We want to take advantage of remote builders to accelerate verification with massively parallel clusters. Using the open source community's tools like Yosys, OpenROAD, Verilator, Surelog etc.\n\nThe vision of this is that this repository enables `bazel test //mychip/...` and `bazel build //mychip:gds` and in 10 minutes you have verified and emitted a fabricatable design even for the most complex designs.\n\n# Contributing\n\n## Testing\n\nFor testing pull requests please run:\n\n```console\nbazel_rules_hdl$ python tools/test_everything.py\n```\n\nNote: `bazel test ...` does not run the tests in Bazel \"remote\" repositories,\nand `bazel_rules_hdl` bundles together support for several remote repositories\n-- this script serves as a helper for testing them all explicitly.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl%2Fbazel_rules_hdl","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhdl%2Fbazel_rules_hdl","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl%2Fbazel_rules_hdl/lists"}