{"id":24373601,"url":"https://github.com/hdl-registers/hdl-registers","last_synced_at":"2025-04-10T18:42:01.207Z","repository":{"id":209823673,"uuid":"725009974","full_name":"hdl-registers/hdl-registers","owner":"hdl-registers","description":"An open-source HDL register code generator fast enough to run in real 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Design"],"sub_categories":[],"readme":".. image:: https://hdl-registers.com/logos/banner.png\n  :alt: Project banner\n  :align: center\n\n|\n\n.. |pic_website| image:: https://hdl-registers.com/badges/website.svg\n  :alt: Website\n  :target: https://hdl-registers.com\n\n.. |pic_repository| image:: https://hdl-registers.com/badges/repository.svg\n  :alt: Repository\n  :target: https://github.com/hdl-registers/hdl-registers\n\n.. |pic_chat| image:: https://hdl-registers.com/badges/chat.svg\n  :alt: Chat\n  :target: https://github.com/hdl-registers/hdl-registers/discussions\n\n.. |pic_pip_install| image:: https://hdl-registers.com/badges/pip_install.svg\n  :alt: pypi\n  :target: https://pypi.org/project/hdl-registers/\n\n.. |pic_license| image:: https://hdl-registers.com/badges/license.svg\n  :alt: License\n  :target: https://hdl-registers.com/rst/about/license_information.html\n\n.. |pic_ci_status| image:: https://github.com/hdl-registers/hdl-registers/actions/workflows/ci.yml/badge.svg?branch=main\n  :alt: CI status\n  :target: https://github.com/hdl-registers/hdl-registers/actions/workflows/ci.yml\n\n.. |pic_python_line_coverage| image:: https://hdl-registers.com/badges/python_coverage.svg\n  :alt: Python line coverage\n  :target: https://hdl-registers.com/python_coverage_html\n\n|pic_website| |pic_repository| |pic_pip_install| |pic_license| |pic_chat| |pic_ci_status|\n|pic_python_line_coverage|\n\nThe hdl-registers project is an open-source HDL register interface code generator fast enough to run\nin real time.\nIt makes FPGA/ASIC development more fun by automating a lot of time-consuming manual work.\nIt also minimizes the risk of bugs by removing the need for duplicate information.\n`Read more \u003chttps://hdl-registers.com/rst/about/about.html\u003e`_\n\n**See documentation on the website**: https://hdl-registers.com\n\nThe following features are supported:\n\n* Register fields\n\n  * `Bit \u003chttps://hdl-registers.com/rst/field/field_bit.html\u003e`_.\n  * `Signed/unsigned fixed-point bit vector \u003chttps://hdl-registers.com/rst/field/field_bit_vector.html\u003e`_.\n  * `Enumeration \u003chttps://hdl-registers.com/rst/field/field_enumeration.html\u003e`_.\n  * `Positive/negative-range integer \u003chttps://hdl-registers.com/rst/field/field_integer.html\u003e`_.\n\n* `Register arrays \u003chttps://hdl-registers.com/rst/basic_feature/basic_feature_register_array.html\u003e`_.\n* `Default registers \u003chttps://hdl-registers.com/rst/basic_feature/basic_feature_default_registers.html\u003e`_.\n* `Register constants \u003chttps://hdl-registers.com/rst/constant/constant_overview.html\u003e`_.\n\nRegisters can be defined using\na `TOML/JSON/YAML data file \u003chttps://hdl-registers.com/rst/user_guide/toml_format.html\u003e`_\nor the `Python API \u003chttps://hdl-registers.com/rst/user_guide/user_guide_python_api.html\u003e`_.\nThe following code can be generated:\n\n* `VHDL \u003chttps://hdl-registers.com/rst/generator/generator_vhdl.html\u003e`_\n\n  * AXI-Lite register file wrapper using records and native VHDL types for values.\n  * Simulation support packages for compact read/write/wait/checking of register and field values.\n\n* `SystemVerilog \u003chttps://hdl-registers.com/rst/generator/generator_systemverilog.html\u003e`_\n\n  * AXI-Lite register file using structures and native types to represent field values.\n\n* `C++ \u003chttps://hdl-registers.com/rst/generator/generator_cpp.html\u003e`_\n\n  * Complete class with setters and getters for registers and fields.\n    Uses structs and native C++ representation of values.\n  * Includes an abstract interface header for unit test mocking.\n\n* `C header \u003chttps://hdl-registers.com/rst/generator/generator_c.html\u003e`_\n  with register addresses and field information.\n\n* `HTML \u003chttps://hdl-registers.com/rst/generator/generator_html.html\u003e`_\n  website with documentation of registers and fields.\n\n* `Python \u003chttps://hdl-registers.com/rst/generator/generator_python.html\u003e`_\n  class with methods to read/write/print each register and field on a target device.\n\nThe tool can also be extended by\n`writing your own code generator \u003chttps://hdl-registers.com/rst/extensions/extensions_custom_generator.html\u003e`_\nusing a simple but powerful API.\n\nThis project is mature and used in many production environments.\nThe maintainers place high focus on quality, with everything having good unit test coverage and a\nthought-out structure.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-registers%2Fhdl-registers","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhdl-registers%2Fhdl-registers","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-registers%2Fhdl-registers/lists"}