{"id":20489807,"url":"https://github.com/hdl-util/gray-code","last_synced_at":"2026-02-01T15:35:05.026Z","repository":{"id":240723548,"uuid":"266413207","full_name":"hdl-util/gray-code","owner":"hdl-util","description":"Generate a gray code of arbitrary width in SystemVerilog","archived":false,"fork":false,"pushed_at":"2020-06-27T22:22:32.000Z","size":10,"stargazers_count":4,"open_issues_count":1,"forks_count":1,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-06-09T15:09:06.254Z","etag":null,"topics":["code","coding","fpga","gray","gray-code","graycode","systemverilog"],"latest_commit_sha":null,"homepage":"https://purisa.me/blog/arbitrary-width-gray-codes/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hdl-util.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE-APACHE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-05-23T20:21:40.000Z","updated_at":"2025-01-13T22:26:23.000Z","dependencies_parsed_at":"2024-05-20T18:22:19.070Z","dependency_job_id":null,"html_url":"https://github.com/hdl-util/gray-code","commit_stats":null,"previous_names":["hdl-util/gray-code"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/hdl-util/gray-code","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fgray-code","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fgray-code/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fgray-code/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fgray-code/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hdl-util","download_url":"https://codeload.github.com/hdl-util/gray-code/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fgray-code/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28981164,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-01T13:38:33.235Z","status":"ssl_error","status_checked_at":"2026-02-01T13:38:32.912Z","response_time":56,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["code","coding","fpga","gray","gray-code","graycode","systemverilog"],"created_at":"2024-11-15T17:14:14.680Z","updated_at":"2026-02-01T15:35:05.001Z","avatar_url":"https://github.com/hdl-util.png","language":"SystemVerilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Gray code\n\n[![Build Status](https://travis-ci.com/hdl-util/gray-code.svg?branch=master)](https://travis-ci.com/hdl-util/gray-code)\n\nSystemVerilog code for generating a [Gray code](https://en.wikipedia.org/wiki/Gray_code) of arbitrary width.\n\n## Why?\n\nI needed an efficient, easy way to generate gray codes for dual clock FIFOs. It's a pain to manually write out a gray code. Why not let a module do the heavy lifting for you?\n\n## Usage\n\n\n1. Take files from `src/` and add them to your own project. If you use [hdlmake](https://hdlmake.readthedocs.io/en/master/), you can add this repository itself as a remote module.\n1. Other helpful modules are also available in this GitHub organization.\n1. Consult the testbench in `test/gray_code_tb.sv` for example usage.\n1. Read through the parameter descriptions in `gray_code.sv` and tailor any instantiations to your situation.\n1. Please create an issue if you run into a problem or have any questions.\n\n## To-do List\n\n* [ ] [Balanced gray codes](https://github.com/hdl-util/gray-code/issues/1)\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-util%2Fgray-code","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhdl-util%2Fgray-code","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-util%2Fgray-code/lists"}