{"id":13537217,"url":"https://github.com/hdl-util/i2c","last_synced_at":"2026-03-09T13:41:12.891Z","repository":{"id":47955953,"uuid":"240324749","full_name":"hdl-util/i2c","owner":"hdl-util","description":"Fully featured implementation of Inter-IC (I2C) bus master for FPGAs","archived":false,"fork":false,"pushed_at":"2020-05-17T22:14:01.000Z","size":119,"stargazers_count":24,"open_issues_count":0,"forks_count":2,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-01-16T05:14:31.752Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"https://purisa.me/blog/mipi-camera-progress/","language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hdl-util.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE-APACHE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-02-13T17:51:09.000Z","updated_at":"2025-01-13T22:26:15.000Z","dependencies_parsed_at":"2022-08-12T15:10:13.315Z","dependency_job_id":null,"html_url":"https://github.com/hdl-util/i2c","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fi2c","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fi2c/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fi2c/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fi2c/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hdl-util","download_url":"https://codeload.github.com/hdl-util/i2c/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":242067713,"owners_count":20066751,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:56.431Z","updated_at":"2026-03-09T13:41:12.841Z","avatar_url":"https://github.com/hdl-util.png","language":"SystemVerilog","funding_links":[],"categories":["Connectivity"],"sub_categories":[],"readme":"# i2c\n\n[![Build Status](https://travis-ci.com/hdl-util/i2c.svg?branch=master)](https://travis-ci.com/hdl-util/i2c)\n\nSystemVerilog code for [I2C](https://en.wikipedia.org/wiki/I%C2%B2C) master/slave on an [FPGA](https://simple.wikipedia.org/wiki/Field-programmable_gate_array).\n\n## Usage\n\n\n1. Take files from `src/` and add them to your own project. If you use [hdlmake](https://hdlmake.readthedocs.io/en/master/), you can add this repository itself as a remote module.\n1. Other helpful modules are also available in this GitHub organization.\n1. Consult the usage example in [i2c-demo](https://github.com/hdl-util/i2c-demo) for code that runs a demo over HDMI.\n1. Read through the parameters in `i2c_master.sv`/`i2c_slave.sv` and tailor any instantiations to your situation.\n1. Please create an issue if you run into a problem or have any questions.\n\n### To-do List\n\n- Master\n    - [x] SCL\n        - [x] Clock stretching\n        - [x] Clock synchronization (multi-master)\n            - [ ] Handle early counter reset\n        - [x] Stuck LOW line detection (bus clear via HW reset or Power-On Reset)\n        - [x] Release line when bus is free / in use by another master\n        - [x] Conformity to stop/repeated start setup \u0026 hold times\n    - [x] SDA\n        - [x] Transmit\n        - [x] Receive\n        - [x] Arbitration (multi-master) (untested)\n            - [x] Basic Implementation\n            - [x] Detect other masters triggering start before this master\n        - [ ] Hotloading (not from i2c spec)\n            - [ ] Self\n                - compensating for jitter of wires connecting/disconnecting... (Schmitt enough?)\n                - listen for WAIT_TIME_END to see if the clock is driven LOW\n                - if no: bus is free\n                - if yes: keep listening until a STOP or START\n            - [x] Other masters (untested)\n                - [x] erroneous starts detected w/ start_err\n    - [x] Port map\n- Slave\n    - [ ] SCL\n    - [ ] SDA\n- Speeds\n    - [x] Standard-mode\n    - [x] Fast-mode\n    - [x] Fast-mode Plus\n    - [ ] High-speed mode\n    - [ ] Ultra Fast-mode\n- [ ] MIPI I3C\n\n\n## Reference Documents\n\nThese documents are not hosted here! They are available on Library Genesis and at other locations.\n\n- [I2C Specification](https://www.nxp.com/docs/en/user-guide/UM10204.pdf)\n- [Understanding the I2C Bus](http://www.ti.com/lit/an/slva704/slva704.pdf)\n- [MIPI I3C Specification](https://b-ok.cc/book/3710131/fc48ef)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-util%2Fi2c","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhdl-util%2Fi2c","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-util%2Fi2c/lists"}