{"id":20489851,"url":"https://github.com/hdl-util/sdram-controller","last_synced_at":"2026-03-11T14:31:35.226Z","repository":{"id":240723539,"uuid":"257099814","full_name":"hdl-util/sdram-controller","owner":"hdl-util","description":"Generic FPGA SDRAM controller, originally made for AS4C4M16SA","archived":false,"fork":false,"pushed_at":"2020-09-07T03:09:41.000Z","size":1611,"stargazers_count":79,"open_issues_count":0,"forks_count":11,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-01-16T05:14:41.174Z","etag":null,"topics":["as4c4m16sa","controller","dram","fpga","quartus","sdram","systemverilog"],"latest_commit_sha":null,"homepage":"https://purisa.me/blog/mipi-camera-progress/","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hdl-util.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":".github/FUNDING.yml","license":"LICENSE-APACHE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null},"funding":{"github":["sameer"]}},"created_at":"2020-04-19T20:52:10.000Z","updated_at":"2024-11-20T01:42:59.000Z","dependencies_parsed_at":"2024-05-20T18:22:15.297Z","dependency_job_id":null,"html_url":"https://github.com/hdl-util/sdram-controller","commit_stats":null,"previous_names":["hdl-util/sdram-controller"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fsdram-controller","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fsdram-controller/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fsdram-controller/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hdl-util%2Fsdram-controller/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hdl-util","download_url":"https://codeload.github.com/hdl-util/sdram-controller/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":242067714,"owners_count":20066751,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["as4c4m16sa","controller","dram","fpga","quartus","sdram","systemverilog"],"created_at":"2024-11-15T17:14:24.406Z","updated_at":"2026-03-11T14:31:35.177Z","avatar_url":"https://github.com/hdl-util.png","language":"Verilog","funding_links":["https://github.com/sponsors/sameer"],"categories":[],"sub_categories":[],"readme":"# Generic Synchronous DRAM Controller\n\n[![Build Status](https://travis-ci.com/hdl-util/sdram-controller.svg?branch=master)](https://travis-ci.com/hdl-util/sdram-controller)\n\n## Why?\n\nThe code in this repository lets you control an SDRAM chip without licensing IP from anyone.\n\n### Demo: test pattern on an LG 24UD58-B Monitor\n\n![Test pattern shown correctly](demo.jpg)\n\n## Usage\n\n1. Take files from `src/` and add them to your own project. If you use [hdlmake](https://hdlmake.readthedocs.io/en/master/), you can add this repository itself as a remote module.\n1. Other helpful modules are also available in this GitHub organization.\n1. See `top/mkrvidor4000_quartus/mkrvidor4000_top.sv` for a usage example with clock domain crossing. A dual-clock FIFO is used to move data from the SDRAM to HDMI to display a test pattern. The test pattern is composed only of red and green. If you see blue, the pattern is incorrect.\n1. Read through the parameters in `sdram_controller.sv` and tailor any instantiations to your situation.\n1. Please create an issue if you run into a problem or have any questions. Make sure you have consulted the troubleshooting section first.\n\n### Terminology\n\n* **CAS latency**: the time (in clocks) after the column-address is set for the command to return data\n* **Precharge**: a required step in DRAM operation that sets the line voltage to Vcc / 2 (3.3V / 2) in anticipation of the next operation\n* **Refresh**: restores the charge in the cells by rewriting them, preventing the loss of data\n* **Self Refresh**: a low power mode where the SDRAM chip is able to refresh itself\n* **DQM**: turning on DQ-masking disables the output during a read and masks the input during a write. Used to avoid I/O contention.\n\n### Troubleshooting\n\n* Make sure you've set the IO standard for the pins connected to the DRAM chip as LVTTL 3.3V\n* SystemVerilog users: make sure you are using `wire` instead of `logic` for DQ and the clock. This caused synthesis issues for me where the pins were stuck at GND or VCC when they were clearly being driven.\n* If you see noise or data corruption, check your FPGA driver strength, check if the SDRAM chip has configurable driver strength, and try lowering the clock\n\n## To-do List\n\n* Self Refresh Mode\n* Optimizations\n    * [x] Conditionally avoid manual precharging\n        * Manual precharging can assume spatial locality by only precharging if the next command is for a different column-address\n    * [x] Bank activation: if the row address and bank are the same, can you do a repeated read/write? (yes until tmax bank active)\n    * [ ] Command pipelining: you could activate another bank while a write/read is being done (some overhaul of the state machine is needed here)\n\n\n## Reference Documents\n\nThese documents are not hosted here! They are available directly from Alliance Memory.\n\n* [AS4C4M16SA 6 or 7 Datasheet](https://www.alliancememory.com/wp-content/uploads/pdf/dram/64M-AS4C4M16SA-CI_v3.0_March%202015.pdf)\n* [AS4C4M16SA 5 Datasheet](https://www.alliancememory.com/wp-content/uploads/pdf/dram/AllianceMemory-64M_SDRAM_A_Rev_AS4C4M16SA-5TCN_December2016v1.0.pdf)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-util%2Fsdram-controller","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhdl-util%2Fsdram-controller","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhdl-util%2Fsdram-controller/lists"}