{"id":38210115,"url":"https://github.com/hell03end/verilog-uart","last_synced_at":"2026-01-17T00:42:04.036Z","repository":{"id":48627873,"uuid":"135932086","full_name":"hell03end/verilog-uart","owner":"hell03end","description":"Simple 8-bit UART realization on Verilog HDL.","archived":false,"fork":false,"pushed_at":"2022-07-23T12:04:31.000Z","size":1429,"stargazers_count":32,"open_issues_count":5,"forks_count":12,"subscribers_count":1,"default_branch":"master","last_synced_at":"2023-03-07T21:34:32.244Z","etag":null,"topics":["fpga","hdl","quartus","uart","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hell03end.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2018-06-03T19:00:45.000Z","updated_at":"2023-02-17T02:51:57.000Z","dependencies_parsed_at":"2022-09-06T20:51:14.951Z","dependency_job_id":null,"html_url":"https://github.com/hell03end/verilog-uart","commit_stats":null,"previous_names":[],"tags_count":null,"template":null,"template_full_name":null,"purl":"pkg:github/hell03end/verilog-uart","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hell03end%2Fverilog-uart","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hell03end%2Fverilog-uart/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hell03end%2Fverilog-uart/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hell03end%2Fverilog-uart/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hell03end","download_url":"https://codeload.github.com/hell03end/verilog-uart/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hell03end%2Fverilog-uart/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28490461,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-16T23:55:29.509Z","status":"ssl_error","status_checked_at":"2026-01-16T23:55:29.108Z","response_time":107,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","hdl","quartus","uart","verilog"],"created_at":"2026-01-17T00:42:03.547Z","updated_at":"2026-01-17T00:42:04.028Z","avatar_url":"https://github.com/hell03end.png","language":"Verilog","readme":"verilog-uart\n============\nSimple 8-bit UART realization on [Verilog HDL](https://en.wikipedia.org/wiki/Verilog).\n\nAble to operate 8 bits of serial data, one start bit, one stop bit.\n\nUsage\n-----\n![uart](rsc/uart.png)\n\n### Parameters:\n* `CLOCK_RATE` - board internal clock rate\n* `BAUD_RATE` - target baud rate\n\n### IO:\n\n#### control:\n* `clk` - **[input]** board internal clock\n\n#### rx interface:\n* `rx` - **[input]** receiver input\n* `rxEn` - **[input]** enable/disable receiver\n* `out[7..0]` - **[output]** received data\n* `rxDone` - **[output]** end of transaction (1 posedge clk)\n* `rxBusy` - **[output]** transaction is in progress\n* `rxErr` - **[output]** transaction error: invalid start/stop bit (1 posedge clk)\n\n#### tx interface:\n* `txEn` - **[input]** enable/disable transmitter\n* `txStart` - **[input]** start of transaction (1 posedge clk)\n* `in[7..0]` - **[input]** data to transmit (stored inside while transaction is in progress)\n* `tx` - **[output]** transmitter output\n* `txDone` - **[output]** end of transaction (1 posedge clk)\n* `txBusy` - **[output]** transaction is in progress\n\nDemo\n----\n![structure](rsc/uart_structure.png)\n\nUart functional modeling on:\n* `CLOCK_RATE=32`\n* `BAUD_RATE=1`\n* `T(clk) = 0.5us`\n* `T(rxEn) = 800us`\n* `T(rx) = 128us`\n* `T(txEn) = 700us`\n* `T(txStart) = 200us`\n* `T(in) = 30us` (counter inc by 1)\n\n![uart functional modeling](rsc/uart_func_model.png)\n\nReceiver functional modeling on:\n* `T(clk) = 1us`\n* `en=1`\n* `T(rx) = 144us`\n\n![receiver functional modeling](rsc/rx_func_model.png)\n\nTransmitter functional modeling on:\n* `T(clk) = 1us`\n* `en=1`\n* `T(start) = 200us`\n* `T(in) = 30us` (counter inc by 1)\n\n![transmitter functional modeling](rsc/tx_func_model.png)\n\nBaud rate generator functional modeling on:\n* `CLOCK_RATE=32`\n* `BAUD_RATE=1`\n* `T(clk) = 0.5us`\n\n![baud rate generator functional modeling](rsc/baud_gen_func_model.png)\n\n\nTODO\n----\n* testbench\n* parameter to control data width\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhell03end%2Fverilog-uart","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhell03end%2Fverilog-uart","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhell03end%2Fverilog-uart/lists"}