{"id":20984375,"url":"https://github.com/hellokenlee/embeddedsystem","last_synced_at":"2026-04-06T06:02:32.137Z","repository":{"id":24139374,"uuid":"27528605","full_name":"hellokenlee/EmbeddedSystem","owner":"hellokenlee","description":"Labs for EmbeddedSystem, wirte with verilog","archived":false,"fork":false,"pushed_at":"2015-01-08T14:27:57.000Z","size":212,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"master","last_synced_at":"2026-01-01T01:14:10.668Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":"axi0mX/ipwndfu","license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hellokenlee.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2014-12-04T07:25:48.000Z","updated_at":"2015-01-08T14:27:58.000Z","dependencies_parsed_at":"2022-08-22T12:10:06.716Z","dependency_job_id":null,"html_url":"https://github.com/hellokenlee/EmbeddedSystem","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/hellokenlee/EmbeddedSystem","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hellokenlee%2FEmbeddedSystem","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hellokenlee%2FEmbeddedSystem/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hellokenlee%2FEmbeddedSystem/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hellokenlee%2FEmbeddedSystem/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hellokenlee","download_url":"https://codeload.github.com/hellokenlee/EmbeddedSystem/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hellokenlee%2FEmbeddedSystem/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31461534,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-05T21:22:52.476Z","status":"online","status_checked_at":"2026-04-06T02:00:07.287Z","response_time":112,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-11-19T05:53:20.808Z","updated_at":"2026-04-06T06:02:32.110Z","avatar_url":"https://github.com/hellokenlee.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"Embedded System Architecture Design\n==============\n\nLabs for EmbeddedSystem, wirte with verilog\n\n==============\n\nLab Environment:\n    - Xilinx ISE 12.3 in Ubuntu 14.4LTS\n    - Digilent NEXYS3 Board(with Xilinx Spartan -6)\n\n==============\n\nFileSystem:\n  -projectName/\u003cbr\u003e\n  |\u003cbr\u003e\n  ------------project.v\u003cbr\u003e\n  |\u003cbr\u003e\n  ------------projectTest.v\u003cbr\u003e\n  |\u003cbr\u003e\n  ------------projectConstrains.ufc\u003cbr\u003e\n\n==============\n\nBuild Method:\n  - in Xilinx ISE 12.3 new a project\n  - new a source, choose Verilog Module\n  - copy project.v to the new file\n  - (optional) new a source, choose Verilog Test Fixture\n  - (optional) copy projectTest.v to the new file\n  - (optional) choose the TestFile, click ISIM Simulator to run Test\n  - new a source, choose Implementation Constraints\n  - copy the projectConstrains.ucf to the file\n  - click Generate Programming File and wait...\n  - if the light turn Green,it success\n  - open a terminal, cd to your project dir\n  - connect to the NEXYS3 Board\n  - run \"djtgcfg prog -d Nexys3 -i 0 -f project.bit\" to download the programm\n  - then you will see the design is onBoard working!\n  \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhellokenlee%2Fembeddedsystem","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhellokenlee%2Fembeddedsystem","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhellokenlee%2Fembeddedsystem/lists"}