{"id":16696472,"url":"https://github.com/hsluoyz/atalanta","last_synced_at":"2026-03-27T04:20:36.337Z","repository":{"id":99865275,"uuid":"9771719","full_name":"hsluoyz/Atalanta","owner":"hsluoyz","description":"Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.","archived":false,"fork":false,"pushed_at":"2024-05-07T15:09:57.000Z","size":34711,"stargazers_count":77,"open_issues_count":9,"forks_count":35,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-01-20T21:50:15.645Z","etag":null,"topics":["atalanta","atpg","verilog","vlsi"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hsluoyz.png","metadata":{"files":{"readme":"README","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2013-04-30T13:36:52.000Z","updated_at":"2024-12-25T16:04:37.000Z","dependencies_parsed_at":"2024-11-19T18:54:57.500Z","dependency_job_id":null,"html_url":"https://github.com/hsluoyz/Atalanta","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hsluoyz%2FAtalanta","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hsluoyz%2FAtalanta/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hsluoyz%2FAtalanta/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hsluoyz%2FAtalanta/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hsluoyz","download_url":"https://codeload.github.com/hsluoyz/Atalanta/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243511197,"owners_count":20302520,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["atalanta","atpg","verilog","vlsi"],"created_at":"2024-10-12T17:28:55.039Z","updated_at":"2025-12-27T23:21:12.230Z","avatar_url":"https://github.com/hsluoyz.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"\n***********************************************************************\n\nWelcome to ATALANTA \u003cVersion 2.0\u003e!\n\nATALANTA is an automatic test pattern generator for stuck-at faults\nin combinational circuits. It employs the FAN algorithm for test \npattern generation and the parallel pattern single fault propagation \ntechnique for fault simulation. \n\nATALANTA was developed in the Bradley Department of Electrical\nand Computer Engineering, Virginia Polytechnic Institute \u0026 State University\n(VPI\u0026SU) and the copy right belongs to VPI\u0026SU.\nThe source code is released for teaching and research use only. \nAny publication in which ATALANTA was used to obtain the results should\ncite the reference given below. (Please do not say that a public domain\ntool was used in this research.)\n\nThis program, or any derivative thereof, may not be reproduced\nnor used for any commercial product without a written permission form\nfrom Prof. Dong S. Ha. For commercial use of ATALANTA or if any bugs found, \nplease contact to\n\n\tProf. Dong S. Ha\n\tDepartment of Electrical and Computer Eng.\n\tVirginia Tech\n\tBlacksburg, VA 24061\n\n        Ph.: (540) 231-4942\n        Fax: (540) 231-3362\n        E-Mail: ha@vt.edu\n        Web: http://www.ee.vt.edu/ha\n\n************************************************************************\n\nREFERENCE: H. K. Lee and D. S. Ha, \"On the Generation of Test Patterns \n\t   for Combinational Circuits,\" Technical Report No. 12_93,\n\t   Dep't of Electrical Eng., Virginia Polytechnic Institute\n           and State University.\n\n\n***************************** HISTORY **********************************\n\n    atalanta: version 1.0\n\n        Original: H. K. Lee, 8/15/1990\n\n    atalanta: version 1.1\n\n        Shuffling Compaction, Sarita Thakar 12/15/93\n        Added learning, dynamic unique path sensitization, H. K. Lee, 4/30/1994\n        Read the fault list file, H. K. Lee, 4/30/1994\n\n    atalanta: version 2.0           \n        Removed the option -I, H. K. Lee, 6/30/1997\n        Combined HOPE and atalanta, H. K. Lee, 6/30/1997\n            (Added options: -H, -0, -1, -X, -R)\n        Added diagnostic options, H. K. Lee, 6/30/1997\n            (Added options: -A, -D, -Z, -N)\n\n    ********************** Important Note **********************\n    *                                                          *\n    *  Atalanta reads circuits in ISCAS89 netlist format       *\n    *  rather than the original ISCAS85 netlist format.        *\n    *  This is done so, since ISCAS89 netlist format is more   *\n    *  flexible.                                               *\n    *                                                          *\n    ************************************************************\n\n************************************************************************\n\n----------------- Installation Procedure -----------------------------\n\nI.  To install atalanta, follow the procedures described below.\n \n    1. To install atalanta, make a bin directory under your home\n       directory. Suppose that the home directory is ~cad and\n       the source code of atalanta is under the directory\n       ~cad/atalanta.\n \n    2. Go to the directory atalanta using\n       \"cd ~cad/atalanta\".\n \n    3. To compile atalanta, type \"make\".\n       An execution file \"atalanta\" will be created.\n \n    4. Copy or symbolically link atalanta to the directory ~cad/bin using\n       \"cp atalanta ~cad/bin\" or\n       \"ln -s atalanta ~cad/bin\".\n \n \nII. Before using atalanta, each user should set the following\n    two environment variables as described below.\n \n    1. Set your path (or PATH) environment variable to include\n       ~cad/bin in your search path. This variable, in general,\n       can be found in your \".cshrc\" file. For example, the line\n \n       set path = (... ~cad/bin ...)\n \n       includes ~cad/bin to your search path.\n \n    2. Set the ATALANTA_MAN environment variable to indicate the\n       directory atalanta, where the on-line manual of atalanta is \n       located, using the setenv statement as shown below.\n \n       \"setenv ATALANTA_MAN ~cad/atalanta\"\n \n       If you use atalanta frequently, add the above statement to your\n       \".cshrc\" file.\n\n\nRun atalanta as described below.\n\n\n\n----------------- User's Guide for ATALANTA --------------------------\n\nNAME:\tatalanta --- Automatic Test Pattern Generator for stuck-at \n\t\t     faults in combinational circuits\n\nSYNOPSIS: atalanta [options] circuit_file [\u003e outfile]\n\nOPTIONS: Several options are available for atalanta.\n         If an option is not specified, the default value is used.\n\n-A       Diagnostic mode\n         Atalanta derives all test patterns for each fault.\n         In this option, all unspecified inputs are left unknown, and\n         fault simulation is not performed.\n         (default: Normal test generation mode)\n-D n     Diagnostic mode\n         Atalanta derives n test patterns for each fault.\n         In this option, all unspecified inputs are left unknown, and\n         fault simulation is not performed. If both -A and -D option\n         are specified, -D option is applied.\n         (default: Normal test generation mode)\n-b n\t The number of maximum backtrackings for the FAN \n\t algorithm phase 1. (default: -b 10)\n-B n\t If -B n (n\u003e0) option is specified, atalanta generates test\n\t patterns in two phases. In phase 1, static unique path \n\t sensitization is employed. If the test generation for a\n\t target fault is aborted in phase 1, the test generation\n\t is tried in phase 2. In phase 2, dynamic unique path\n\t sensitization is employed. If n=0, phase 2 is not performed.\n\t If n\u003e0, phase 2 test generation is performed with the\n\t backtrack limit of n.\n\t (default: -B 0, i.e., phase 2 is not performed.)\n-f fn    Faults are read from the file fn. \n\t This option is available only for ISCAS89 netlist format.\n         (default: faults are generated internally.)\n-h f     Displays the fault list format\n-h g     Displays the on-line user's guide.\n-h n     Displays an example netlist format.\n-h t     Displays an example test pattern file.\n-h a     Displays the entire on-line manual file.\n         (default: no manual is displayed)\n-H       HOPE, which is a parallel fault fault simulator, is employed\n         for fault simulation. In this option, three logic values (0, 1\n         and X), instead of two logic values (0 and 1), are employed.\n         Due to the embedding of the unknown logic value and the parallel\n         fault fault simulation algorithm, the test generation time is\n         slower than the default mode.)\n         (default: FSIM, which is a parallel pattern fault simulator,\n         is employed, and two logic values are used.)\n-l fn    Log file is created.\n\t (default: no logfile is created)\n-L       Static learning is performed. (default: no learning)\n-c n     Atalanta compacts test patterns using two different \n         methods: reverse order compaction and shuffling \n         compaction. First, test patterns are applied \n         in the reverse order and fault simulated (reverse order \n         compaction). Second, test patterns are shuffled randomly \n         and fault simulated (shuffling compaction). During the fault \n         simulations, all the test patterns which do not detect a \n         new fault are eliminated. The option -c n specifies \n         the limit of shuffling compaction. If n\u003e0, shuffling \n         compaction is terminated if n consecutive shuffles\n         do not drop a test pattern. If n=0, shuffling\n         compaction is not included and compaction is done only \n         by the reverse order fault simulation.\n         (default: -c 2)\n-N       Test compaction is not performed.\n         (default: -c 2)\n-r n\t Random Pattern Testing (RPT) Session is included before\n\t deterministic test pattern generation session.\n         The RPT session stops if any n consecutive packets of\n         32 random patterns do not detect any new fault.\n\t If n=0, the RPT session is not included.\n\t (default: -r 16)\n-s n\t Initial seed for the random number generator (random()).\n\t If n=0, the initial seed is the current time.\n\t (default: -s 0)\n-t fn    Test patterns are put into the file \"fn\".\n\t (default: *.test for a circuit named *.bench)\n-u       Atalanta prints out all aborted fauts in a file. The name of this\n         file is \u003cckt\u003e.ufaults. In default, all identified redundant faults\n         are not included in the file, but you can include them using the\n         option -v. Note that atalanta does not update a fault file if one\n         already exists in the run directory. This fault list file can\n         be directly read by atalanta or hope.\n         (default: no file is created)\n-U fn    The same as -u, but atalanta writes aborted faults to the given\n         file name.\n         (default: no file is created)\n-v       Atalanta prints out all identified redundant faults as well as\n         aborted fauts in a file. If -U fn option is not given, Atalanta\n         prints out the faults in a default file, \u003cckt\u003e.ufaults.\n         (default: no file is created)\n-Z       Atalanta derives one test pattern for each fault. In this option,\n         no fault simulation is performed during the entire test generation\n         (including random pattern test generation session, deterministic\n         test generation session and test compaction session). All unspecified\n         inputs are left unknown.\n-0, -1, -X, -R: During test generation, some inputs can be unspecified.\n         Atalanta provides various options to set these unspecified inputs\n         into a certain value. The options are described below.\n         -0    Unspecified inputs are set to logic 0.\n         -1    Unspecified inputs are set to logic 1.\n         -R    Unspecified inputs are set to logic 0 or logic 1 randomly.\n         -X    Unspecified inputs are left to unknown (X).\n         (default: -R)\n\nOUTPUTS: In default mode, one file is created. The summary \n\t of the test pattern generation is reported to the \n\t standard output and the test patterns are stored in\n\t the circuit_name.test file. If -l option \n\t is specified, atalanta creates a log file. \n\t The log file contains more detailed information\n\t on the test pattern generation result.\n\nON-LINE HELP: Type atalanta to see the available on-line\n         help command.\n\nEXAMPLES:\n\tatalanta c432.bench\n\t   --- generates test patterns for the circuit c432.bench\n\t       with default options (i.e., the same as\n\t       atalanta -r 16 -R -s 0 -b 10 -B 20 -c 2 -t c432.test \n       \t       c432.bench).\n\t       The generated test patterns are stored in file \n\t       c432.test and the summary of the test pattern\n\t       is reported to the standard output (CRT terminal).\n\n        atalanta -A -f c432.flt c432.bench\n           --- Diagnostic mode run\n               reads the fault list from the file c432.flt, and\n               generates all test patterns for each fault.\n\n        atalanta -D 2 c432.bench\n           --- Diagnostic mode run\n               Generates n test patterns for each fault.\n\n\n\n\nNETLIST FORMAT:\n\n\t      The input netlist format for atalanta is ISCAS89 \n\tnetlist format except for the following two cases.\n\tThe first line should be # followed by the name of \n\tthe circuit. The lines beginning with # excluding\n\tthe first line are comment lines and ignored. These\n\tcomment lines may be put into any part of the netlist.\n\tIt should be noted that the order of gates appearing\n\tin the netlist is not significant.\n\tThe name of gates can be a string of alpha-numeric\n\tcharacters (0-9, A-Z, a-z, _, [, or ]).\n\n\tISCAS85 circuits translated in ISCAS89 netlist\n\tformat are stored in directory ISCAS85. The name of a \n\tcircuit in ISCAS89 netlist format is circuit_name.bench.\n\n\t      Example netlists of the circuit c17 written in\n\tISCAS89 netlist format is shown below.\n\n\nEXAMPLE: ISCAS89 NETLIST FORMAT (c17.bench)\n--------------------------------------------------------------------\n# c17\n# 5 inputs\n# 2 outputs\n# 0 inverters\n# 6 gates ( 6 NANDs )\n\nINPUT(1)\nINPUT(2)\nINPUT(3)\nINPUT(6)\nINPUT(7)\n\nOUTPUT(22)\nOUTPUT(23)\n\n10 = NAND(1, 3)\n11 = NAND(3, 6)\n16 = NAND(2, 11)\n19 = NAND(11, 7)\n22 = NAND(10, 16)\n23 = NAND(16, 19)\n-------------------------------------------------------------------\n\n\n\nMANAGEABLE GATES:\n\n-------------------------------------------------------\n   syntax                   gate type\n-------------------------------------------------------\n   INPUT                    primary input\n   OUTPUT                   primary output\n   AND                      and gate\n   NAND                     nand gate\n   OR                       or gate\n   NOR                      nor gate\n   XOR                      2-input exclusive-or gate\n   BUFF or BUF              buffer\n   NOT                      inverter\n-------------------------------------------------------\n* Gate types can be also written in lower case.\n\n\n\n\nTEST PATTERN FILE:\n\n\t       The line beginning with * is a comment line and\n\tignored. Each test pattern begins after a colon (:).\n\tFor an n input circuit, only the n bits following :\n\tare significant, and the remaining bits, if any, are\n\tignored. The j'th bit of a test pattern is the value \n\tof the j'th input of the circuit (in terms of their\n\tappearance in the circuit). For example, c17 has five\n\tinputs named input1, input2, input3, input6 and input7\n\twhich appear in the order in the netlist. The first bit\n\tof a test pattern is the value for input1, the second \n\tfor input2, ..., and the last for input7.\n\n\nEXAMPLE: TEST PATTERN FILE FOR C17\n\n___________________________________________________________\n* Name of circuit:  c17\n\n   1: 01010\n   2: 11110\n   3: 10101\n   4: 00111\n   5: 10010\n   6: 00101\n__________________________________________________________\n\n\n\nFAULT LIST FILE:\n \n               ATALANTA can read the fault list file supplied\n        by the user. When the option \"-f fn\" is specified,\n        the fault list is read from the file \"fn\". (In default,\n        the fault list is created internally.)\n \n        An example of the fault list file is shown below:\n \n        ------ EXAMPLE: A FAULT LIST FILE ----------------------\n        gate_A-\u003egate_B /1\n        gate_A-\u003egate_B /0\n        gate_A /1\n        gate_B /1\n        bin[2] -\u003e gate_B /1\n        --------------------------------------------------------\n \n               In the above example, gate_A and gate_B are the name\n        of gates. The first line, \"gate_A-\u003egate_B /1\" describes\n        the stuck-at 1 fault on the gate_B input line, which\n        is connected to gate_A. Similarly, the second line,\n        \"gate_A-\u003egate_B /0\" describes the stuck-at 0 fault on the\n        gate B input which is connected to gate_A. The third and\n        fourth lines describe the stuck-at 1 faults on the gate_A\n        output and the gate_B output, respectively. \n \n        ******************* Note **********************************\n        No fault collapsing is performed under the option -f. Hence,\n           users should provide the collapsed fault list.\n        ***********************************************************\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhsluoyz%2Fatalanta","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhsluoyz%2Fatalanta","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhsluoyz%2Fatalanta/lists"}