{"id":21024373,"url":"https://github.com/hukenovs/fp23fftk","last_synced_at":"2025-05-15T08:33:11.241Z","repository":{"id":90537970,"uuid":"82668285","full_name":"hukenovs/fp23fftk","owner":"hukenovs","description":"Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).","archived":false,"fork":false,"pushed_at":"2022-07-05T21:21:58.000Z","size":1333,"stargazers_count":58,"open_issues_count":0,"forks_count":18,"subscribers_count":8,"default_branch":"master","last_synced_at":"2025-04-03T07:07:18.133Z","etag":null,"topics":["altera","chirp","convolution","convolution-filter","cooley-tukey-fft","digital-signal-processing","dsp","fast-convolutions","fast-fourier-transform","fft","floating-point","fpga","frequency-analysis","ieee754","matlab","octave","radix-2","verilog","vhdl","xilinx"],"latest_commit_sha":null,"homepage":null,"language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hukenovs.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2017-02-21T10:42:33.000Z","updated_at":"2025-02-25T10:08:32.000Z","dependencies_parsed_at":null,"dependency_job_id":"92ee0b41-3d9f-4420-8d43-ce598efd42f7","html_url":"https://github.com/hukenovs/fp23fftk","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hukenovs%2Ffp23fftk","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hukenovs%2Ffp23fftk/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hukenovs%2Ffp23fftk/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hukenovs%2Ffp23fftk/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hukenovs","download_url":"https://codeload.github.com/hukenovs/fp23fftk/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254304732,"owners_count":22048455,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","chirp","convolution","convolution-filter","cooley-tukey-fft","digital-signal-processing","dsp","fast-convolutions","fast-fourier-transform","fft","floating-point","fpga","frequency-analysis","ieee754","matlab","octave","radix-2","verilog","vhdl","xilinx"],"created_at":"2024-11-19T11:25:37.051Z","updated_at":"2025-05-15T08:33:06.221Z","avatar_url":"https://github.com/hukenovs.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Floating point (FP23) FFT/IFFT cores\n\nThis project contains **fully pipelined** floating-point FFT/IFFT cores for Xilinx FPGA, Scheme: Radix-2, Decimation in frequency and decimation in time;    \nInteger data type and twiddles with configurable data width. \n**Code language** - VHDL, Verilog \n**Vendor**: Xilinx, 6/7-series, Ultrascale, Ultrascale+;  \n\nLicense: GNU GPL 3.0. \n\n### Main information\n\n| **Title**         | Universal floating point FFT cores (Xilinx FPGAs) |\n| -- | -- |\n| **Author**        | [Alexander Kapitanov](https://habr.com/ru/users/hukenovs/) |\n| **Project lang**  | VHDL, Verilog                              |\n| **Vendor**        | Xilinx: 6/7-series, Ultrascale, US+        |\n| **Release Date**  | 02 Feb 2015                                |\n| **Last Update**   | 27 Jun 2019                                |\n\n#### Floating-point (custom format)\n\nFloating point 23-bit vector (optimized for FPGAs): \n- EXPONENT - 6-bits \n- SIGN - 1-bit \n- MANTISSA - 16+1 bits \n'1' means hidden bit for normalized floating-point values; \n\n#### Math: \n**A = (-1)^sign(A) * 2^(exp(A)-31) * mant(A)**\n\n### List of complements:\n- FFTs:\n   * fp23_fftNk  – main core - Floating-point FFT, Radix-2, DIF, input flow - natural, output flow - bit-reversed. \n   * fp23_ifftNk – main core - Floating-point FFT, Radix-2, DIT, input flow - bit-reversed, output flow - natural.\n\n- Butterflies:\n   * fp23_bfly_fwd – Floating-point butterfly Radix-2, decimation in frequency, \n   * fp23_ibfly_inv – Floating-point butterfly Radix-2, decimation in time. \n\n- Math (in fp23):\n   * fp23_addsub – adder / substractor, \n   * fp23_addsub_dbl – adder and substractor, \n   * fp23_fix2float – int16 to fp23 converter, \n   * fp23_float2fix – fp23 to int16 converter,\n   * fp23_mult – multiplier,\n   * fp23_cmult – complex multiplier.\n\n- Delay line:\n  * fp_delay_line – main delay line, cross-commutation data between butterflies,\n  * fp23fft_align_data – data and twiddle factor alignment for butterflies in FFT core,\n  * fp23ifft_align_data – data and twiddle factor alignment for butterflies in IFFT core.\n\n- Twiddles:\n  * rom_twiddle_int – 1/4-periodic signal, twiddle factor generator based on memory and sometimes uses DSP48 units for large FFTs\n  * row_twiddle_tay – twiddle factor generator which used Taylor scheme for calculation twiddles.\n\n- Buffers:\n  * fp_Ndelay_in  – input delay line (for simple flow with 1 data word in clock cycle),\n  * fp_Ndelay_out – output delay line (for simple flow with 1 data word in clock cycle),\n  * fp_bitrev_ord – converter data from bit-reverse to natural order.\n\n### Fast Convolution:\n- FFTs:\n   * fp23_fconv_core  – main core: Input buffer, Lin Fast Convolution, Output buffer, Support function,\n   * fp23_linconv_dbl – Forward FFT, Inverse FFT, Complex multiplier etc,\n   * fp23_fftNk2_core - Double Path Forward / Inverse Floating-point FFT, Radix-2, DIF/DIT,\n\n- Buffers:\n  * iobuf_fft_hlf2 – delay second part of data for Linear Fast Convolution, \n  * iobuf_fft_int2 – delay first part of data for Linear Fast Convolution, \n  * inbuf_fastconv_int2 – Input buffer for linear fast convolution and interleave-2 data, \n  * int_delay_wrap - delay line for wrap-mode. You don't need collecting NFFT data words. Fully pipelined.\n  * fp23_sfunc_dbl - Support function: two buffers 0/1 can store filter responce into freq domain.\n\n#### How to check Fast Convolution HDL model:\n- Create Vivado project *example.xpr*, select 7-series or Ultrascale/+ FPGA.\n- Add sources from */src* directory to your project.\n- Set testbench file as top for simulation from */src/testbench* dir directory\n- Run Octave / MATLAB *.m* file from *math/* directory. Set **NFFT** and other signal parameters. Change input signal or use my model. After this you will get test file *test_signal.dat* with complex signal.\n- Run simulation into Vivado / Aldec Active-HDL / ModelSim. Set time of simulation \u003e 100 us. For N \u003e 32K set 500 us or more.\n- Return to Octave / MATLAB and run *.m* script again. \n- Compare Fast Convolution: an ideal result in double prec. and HDL results (fp23).\n\n\n### Link (Russian collaborative IT blog)\n  * https://habr.com/ru/post/322728/\n  \n### Authors:\n  * Kapitanov Alexander  \n  \n### First Release:\n  * 2015/02/02\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhukenovs%2Ffp23fftk","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhukenovs%2Ffp23fftk","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhukenovs%2Ffp23fftk/lists"}