{"id":28372470,"url":"https://github.com/hvardhan1437/eoc-assignment-4","last_synced_at":"2025-10-04T09:58:02.891Z","repository":{"id":256392650,"uuid":"583725830","full_name":"hvardhan1437/EOC-ASSIGNMENT-4","owner":"hvardhan1437","description":"Implementation of digital logic circuits for EOC Assignment 4 using HDL-style modules, based on the Nand2Tetris curriculum. Includes gates, multiplexers, demultiplexers, and adders.","archived":false,"fork":false,"pushed_at":"2025-04-22T12:17:46.000Z","size":4,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2025-05-29T15:57:07.329Z","etag":null,"topics":["adder-circuits","combinational-logic","demultiplexer","digital-logic","elements-of-computing-systems","full-adder","half-adder","hdl","logic-gates","multiplexer","nand2tetris"],"latest_commit_sha":null,"homepage":"","language":"MATLAB","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hvardhan1437.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-12-30T17:52:08.000Z","updated_at":"2025-04-22T12:41:33.000Z","dependencies_parsed_at":"2024-09-10T13:37:29.209Z","dependency_job_id":"929e0ec1-fb9c-45ba-81d8-795849c93268","html_url":"https://github.com/hvardhan1437/EOC-ASSIGNMENT-4","commit_stats":null,"previous_names":["hvardhan1437/eoc-assignment-4"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/hvardhan1437/EOC-ASSIGNMENT-4","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hvardhan1437%2FEOC-ASSIGNMENT-4","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hvardhan1437%2FEOC-ASSIGNMENT-4/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hvardhan1437%2FEOC-ASSIGNMENT-4/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hvardhan1437%2FEOC-ASSIGNMENT-4/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hvardhan1437","download_url":"https://codeload.github.com/hvardhan1437/EOC-ASSIGNMENT-4/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hvardhan1437%2FEOC-ASSIGNMENT-4/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":278296084,"owners_count":25963432,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-04T02:00:05.491Z","response_time":63,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["adder-circuits","combinational-logic","demultiplexer","digital-logic","elements-of-computing-systems","full-adder","half-adder","hdl","logic-gates","multiplexer","nand2tetris"],"created_at":"2025-05-29T15:40:23.936Z","updated_at":"2025-10-04T09:58:02.886Z","avatar_url":"https://github.com/hvardhan1437.png","language":"MATLAB","funding_links":[],"categories":[],"sub_categories":[],"readme":"\n# 💻 EOC Assignment 4 – Elements of Computing Systems\nThis repository contains the implementation for Assignment 4 of the subject Elements of Computing Systems. It focuses on designing and simulating key digital logic components using a minimalist hardware description style inspired by the Nand2Tetris curriculum.\n\n# 📁 Repository Contents\n-\u003eHDL-style logic modules implemented as .m files\n\n-\u003eCustom-built logic gates and combinational components:\n\n * AND, OR, NOT gates\n\n * Multiplexers (2:1, 4:1, 8:1)\n\n * Demultiplexers (1:2, 1:4)\n\n * Adders (Half Adder, Full Adder, 4-bit Adder)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhvardhan1437%2Feoc-assignment-4","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhvardhan1437%2Feoc-assignment-4","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhvardhan1437%2Feoc-assignment-4/lists"}