{"id":48217618,"url":"https://github.com/hw-bzl/rules_verilator","last_synced_at":"2026-04-04T19:01:39.671Z","repository":{"id":328771703,"uuid":"1116641357","full_name":"hw-bzl/rules_verilator","owner":"hw-bzl","description":"Bazel rules for Verilator-based SystemVerilog simulation using the Bazel Central Registry (BCR) Verilator toolchain.","archived":false,"fork":false,"pushed_at":"2026-03-29T12:52:51.000Z","size":91,"stargazers_count":3,"open_issues_count":1,"forks_count":1,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-03-31T00:28:27.004Z","etag":null,"topics":["bazel","bazel-rules","simulation","verilator"],"latest_commit_sha":null,"homepage":"https://registry.bazel.build/modules/rules_verilator","language":"Starlark","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/hw-bzl.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-12-15T07:05:48.000Z","updated_at":"2026-03-29T12:42:36.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/hw-bzl/rules_verilator","commit_stats":null,"previous_names":["mrams/bazel_rules_verilator","hw-bzl/rules_verilator"],"tags_count":3,"template":false,"template_full_name":null,"purl":"pkg:github/hw-bzl/rules_verilator","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hw-bzl%2Frules_verilator","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hw-bzl%2Frules_verilator/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hw-bzl%2Frules_verilator/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hw-bzl%2Frules_verilator/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/hw-bzl","download_url":"https://codeload.github.com/hw-bzl/rules_verilator/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/hw-bzl%2Frules_verilator/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31409471,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-04T10:20:44.708Z","status":"ssl_error","status_checked_at":"2026-04-04T10:20:06.846Z","response_time":60,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["bazel","bazel-rules","simulation","verilator"],"created_at":"2026-04-04T19:01:38.924Z","updated_at":"2026-04-04T19:01:39.652Z","avatar_url":"https://github.com/hw-bzl.png","language":"Starlark","funding_links":[],"categories":[],"sub_categories":[],"readme":"# rules_verilator\n\n[![BCR](https://img.shields.io/badge/BCR-rules_verilator-green?logo=bazel)](https://registry.bazel.build/modules/rules_verilator)\n[![CI](https://github.com/MrAMS/bazel_rules_verilator/actions/workflows/ci.yml/badge.svg)](https://github.com/MrAMS/bazel_rules_verilator/actions/workflows/ci.yml)\n\nBazel rules for Verilator-based SystemVerilog simulation using the Bazel Central Registry (BCR) Verilator toolchain.\n\n## Features\n\n- Uses BCR Verilator for better reproducibility and version management\n- Supports both C++ and SystemC output\n- Support incremental hierarchical builds\n- Optional waveform tracing support\n- Compatible with Bazel 7.5.0+\n\n## Installation\n\n### Default Installation (C++ Only)\n\nAdd the following to your `MODULE.bazel`:\n\n```starlark\nbazel_dep(name = \"rules_verilator\", version = \"0.3.1\")\nbazel_dep(name = \"verilator\", version = \"5.044\")\nregister_toolchains(\n    \"@rules_verilator//verilator:verilator_toolchain\",\n)\n```\n\nThe default toolchain supports C++ output only and does not require SystemC.\n\n### With SystemC Support\n\nIf you need SystemC output, add the SystemC dependency and register the SystemC-enabled toolchain:\n\n```starlark\nbazel_dep(name = \"rules_verilator\", version = \"0.3.1\")\nbazel_dep(name = \"verilator\", version = \"5.044\")\nbazel_dep(name = \"systemc\", version = \"3.0.2\")\n\n# Register the SystemC-enabled toolchain\nregister_toolchains(\n    \"@rules_verilator//verilator:verilator_toolchain_with_systemc\",\n)\n```\n\n\u003e [!TIP]\n\u003e Verilator and SystemC are not bundled with `rules_verilator`. Users must explicitly declare them in their own `MODULE.bazel`. SystemC is **optional** and only required if you set `systemc = True` in your `verilator_cc_library` targets.\n\u003e\n\u003e `rules_verilator` `0.3.0+` requires the refactored `rules_verilog` provider interface (`rules_verilog \u003e= 1.0.0`).\n\n## Usage\n\nYou can check `verilator/tests` for examples as well.\n\n### Verilator C++ Library\n\n```starlark\nload(\"@rules_verilator//verilator:defs.bzl\", \"verilator_cc_library\")\n\nverilator_cc_library(\n    name = \"my_verilated_lib\",\n    module = \":my_module\",\n    module_top = \"my_top_module\",\n    trace = True,  # Enable waveform tracing\n    vopts = [\n        \"-Wall\",\n        \"--x-assign fast\",\n        \"--x-initial fast\",\n    ],\n)\n\ncc_binary(\n    name = \"my_test\",\n    srcs = [\"testbench.cpp\"],\n    deps = [\":my_verilated_lib\"],\n)\n```\n\n### Verilator SystemC Library\n\n```starlark\nload(\"@rules_verilator//verilator:defs.bzl\", \"verilator_cc_library\")\n\nverilator_cc_library(\n    name = \"my_verilated_sc_lib\",\n    module = \":my_module\",\n    module_top = \"my_top_module\",\n    systemc = True,  # Generate SystemC output\n    trace = True,\n    vopts = [\"-Wall\"],\n)\n\ncc_binary(\n    name = \"my_sc_test\",\n    srcs = [\"testbench_sc.cpp\"],\n    deps = [\":my_verilated_sc_lib\"],\n)\n```\n\n### Hierarchical Verilation\n\nFor [verilator's hierarchical verilation](https://verilator.org/guide/latest/verilating.html#hierarchical-verilation), use the dedicated hierarchical rules. The regular `verilator_cc_library` remains unchanged.\n\nThese rules let large designs be verilated block-by-block instead of recompiling the full design on every change, which improves cache reuse, reduces incremental build time, and keeps top-level integration separate from block implementation details.\n\n```starlark\nload(\n    \"@rules_verilator//verilator:defs.bzl\",\n    \"verilator_hierarchical_block_cc_library\",\n    \"verilator_hierarchical_plan\",\n    \"verilator_hierarchical_top_cc_library\",\n)\nload(\"@rules_verilog//verilog:defs.bzl\", \"verilog_library\")\n\nverilog_library(\n    name = \"block_a_sv\",\n    srcs = [\"block_a.sv\"],\n)\n\nverilog_library(\n    name = \"block_b_sv\",\n    srcs = [\"block_b.sv\"],\n)\n\nverilog_library(\n    name = \"top_local_sv\",\n    srcs = [\"top.sv\"],\n)\n\nverilog_library(\n    name = \"full_design_sv\",\n    deps = [\n        \":block_a_sv\",\n        \":block_b_sv\",\n        \":top_local_sv\",\n    ],\n)\n\nverilator_hierarchical_plan(\n    name = \"top_plan\",\n    module = \":full_design_sv\",\n    module_top = \"top\",\n    blocks = [\"block_a\", \"block_b\"],\n)\n\nverilator_hierarchical_block_cc_library(\n    name = \"block_a_verilated\",\n    plan = \":top_plan\",\n    block = \"block_a\",\n    module = \":block_a_sv\",\n)\n\nverilator_hierarchical_block_cc_library(\n    name = \"block_b_verilated\",\n    plan = \":top_plan\",\n    block = \"block_b\",\n    module = \":block_b_sv\",\n)\n\nverilator_hierarchical_top_cc_library(\n    name = \"top_verilated\",\n    plan = \":top_plan\",\n    module = \":top_local_sv\",\n    block_deps = [\n        \":block_a_verilated\",\n        \":block_b_verilated\",\n    ],\n)\n```\n\nNotes:\n- `blocks` is the list of Verilog module names to compile as independent hierarchical blocks.\n- `module` on `verilator_hierarchical_top_cc_library` should contain only top-local sources; keep block sources in their own `verilog_library` targets to preserve cache isolation.\n- The rules auto-generate the temporary `.vlt` hierarchy control file; users do not need to maintain it manually.\n\n## Key Differences from rules_hdl\n\n\u003e [!TIP]\n\u003e This was a fork of the Verilator rules from [hdl/bazel_rules_hdl](https://github.com/hdl/bazel_rules_hdl)\n\n- **No bundled Verilator**: Requires users to declare BCR Verilator dependency explicitly\n- **Optional SystemC**: SystemC is not bundled; users add it only when needed\n- **Bzlmod only**: Designed for MODULE.bazel, not legacy WORKSPACE\n- **Focused scope**: Only Verilator rules, no synthesis/PnR tools\n- **More feature**: Newer version of Verilator, supporting incremental hierarchical builds\n\n## Requirements\n\n- Bazel 7.5.0 or later\n- Verilator 5.036+ from BCR\n- SystemC 3.0.2 from BCR (optional, for SystemC output)\n\n## License\n\nApache License 2.0 (inherited from bazel_rules_hdl)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhw-bzl%2Frules_verilator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fhw-bzl%2Frules_verilator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fhw-bzl%2Frules_verilator/lists"}