{"id":18346703,"url":"https://github.com/infineon/mtb-t2g-example-cpu-mpu-configuration","last_synced_at":"2025-04-09T22:49:58.176Z","repository":{"id":175783806,"uuid":"604016392","full_name":"Infineon/mtb-t2g-example-cpu-mpu-configuration","owner":"Infineon","description":"MTB code example","archived":false,"fork":false,"pushed_at":"2025-02-27T11:55:09.000Z","size":858,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":6,"default_branch":"main","last_synced_at":"2025-02-27T16:23:23.629Z","etag":null,"topics":["additional","kit-t2g-b-h-evk","kit-t2g-b-h-lite","kit-t2g-c-2d-6m-lite","mpu","mtb","protection","t2g-b-h","t2g-c-2d","traveo"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Infineon.png","metadata":{"files":{"readme":"README.md","changelog":"changelog.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-02-20T06:41:15.000Z","updated_at":"2025-02-27T11:55:13.000Z","dependencies_parsed_at":null,"dependency_job_id":"61fc565b-b17c-4cba-8584-be37cd167787","html_url":"https://github.com/Infineon/mtb-t2g-example-cpu-mpu-configuration","commit_stats":null,"previous_names":["infineon/mtb-t2g-example-cpu-mpu-configuration"],"tags_count":5,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Infineon%2Fmtb-t2g-example-cpu-mpu-configuration","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Infineon%2Fmtb-t2g-example-cpu-mpu-configuration/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Infineon%2Fmtb-t2g-example-cpu-mpu-configuration/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Infineon%2Fmtb-t2g-example-cpu-mpu-configuration/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Infineon","download_url":"https://codeload.github.com/Infineon/mtb-t2g-example-cpu-mpu-configuration/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248125636,"owners_count":21051766,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["additional","kit-t2g-b-h-evk","kit-t2g-b-h-lite","kit-t2g-c-2d-6m-lite","mpu","mtb","protection","t2g-b-h","t2g-c-2d","traveo"],"created_at":"2024-11-05T21:12:08.695Z","updated_at":"2025-04-09T22:49:58.154Z","avatar_url":"https://github.com/Infineon.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"\u003cimg src=\"./images/IFX_LOGO_600.gif\" align=\"right\" width=\"150\"/\u003e\n\n# PROT_CPU_MPU_Configuration\n**This code example shows how to configure the Memory Protection Unit (MPU), which is part of the CPU, and describes its operation and initial settings.**  \n\n## Device\nThe device used in this code example (CE) is:\n- [TRAVEO™ T2G CYT4DN Series](https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cortex-microcontroller/32-bit-traveo-t2g-arm-cortex-for-cluster/traveo-t2g-cyt4dn/)\n\n## Board\nThe board used for testing is:\n- TRAVEO™ T2G Cluster 6M Lite kit ([KIT_T2G_C-2D-6M_LITE](https://www.infineon.com/cms/en/product/evaluation-boards/kit_t2g_c-2d-6m_lite/))\n\n## Scope of work\n\nIn this example, the memory is split in different regions and protected. When a protected region is tried to access, an exception is raised.\n\n## Introduction  \n\n**Memory Protection Unit**  \nProtection units in the TRAVEO™ T2G series device enforce security based on different operations. A protection unit allows or restricts bus transfers on the bus infrastructure. The rules are enforced based on specific properties of a transfer.\n\n- An address range that is accessed by the transfer\n\t- Subregion: An address range is partitioned into eight equally-sized subregions and subregion can individual disables\n- Access attributes such as:\n\t- Read/write attribute\n\t- Execute attribute to distinguish a code access from a data access\n\t- User/privilege attribute to distinguish access; for example, OS/kernel access from a task/thread access\n\t- Secure/non-secure attribute to distinguish a secure access from a non-secure access; the Arm Cortex-M CPUs do not \nnatively support this attribute\n\t- A protection context attribute to distinguish accesses from different protection contexts; for Peripheral-DMA (P-DMA) and Memory-DMA (M-DMA), this attribute is extended with a channel identifier, to distinguish accesses from different channels\n- Memory protection\n- Provided by memory protection units (MPUs) and shared memory protection units (SMPUs)\n\t- MPUs distinguish user and privileged accesses from a single bus master\n\t- SMPUs distinguish between different protection contexts and between secure and non-secure accesses\n- Peripheral protection\n\t- Provided by peripheral protection units (PPUs)\n\t- The PPUs distinguish between different protection contexts; they also distinguish secure from non-secure accesses \nand user mode accesses from privileged mode accesses\n- Protection pair structure\n- Software Protection Unit (SWPU): SWPUs define flash write (or erase) permissions, and eFuse read and write \npermissions. An SWPU comprises of the following:\n\t- Flash Write Protection Unit (FWPU)\n\t- eFuse Read Protection Unit (ERPU)\n\t- eFuse Write Protection Unit (EWPU)\n\nMore details can be found in:\n- TRAVEO\u0026trade; T2G CYT4DN\n  - [Technical Reference Manual (TRM)](https://www.infineon.com/dgdl/?fileId=8ac78c8c8691902101869f03007d2d87)\n  - [Registers TRM](https://www.infineon.com/dgdl/?fileId=8ac78c8c8691902101869ef098052d79)\n  - [Data Sheet](https://www.infineon.com/dgdl/?fileId=8ac78c8c869190210186f0cceff43fd0)\n\n## Hardware setup\n\nThis CE has been developed for:\n- TRAVEO\u0026trade; T2G Cluster 6M Lite Kit ([KIT_T2G_C-2D-6M_LITE](https://www.infineon.com/cms/en/product/evaluation-boards/kit_t2g_c-2d-6m_lite/))\u003cBR\u003e\n\n**Figure 1. KIT_T2G_C-2D-6M_LITE (Top View)**\n\n\u003cimg src=\"./images/kit_t2g_c-2d-6m_lite.png\" width=\"800\" /\u003e\u003cBR\u003e\nNo changes are required from the board's default settings.\n\n## Implementation\n\n In this example, the MPU is configured to split the address range into 6 regions with different protection properties:\n \n- Region 0\nBase address: 0x00000000, Size: 4GB, Privileged: No access, User: No access, Execution is permitted\n\n- Region 1\nBase address: 0x10000000, Size: 8 MB, Privileged: Read only, User: Read only, Execution is permitted\n\n- Region 2\nBase address: 0x14000000, Size: 256 KB, Privileged: Read only, User: No access, Execution is not permitted\n\n- Region 3\nBase address: 0x28000000, Size: 1 MB, Privileged: Read/write, User: Read/write, Execution is permitted\n\n- Region 4\nBase address: 0x40000000, Size: 64 MB, Privileged: Read/write, User: Read/write, Execution is not permitted\n\n- Region 5\nBase address: 0xE0000000, Size: 512 MB, Privileged: Read/write, User: Read/write, Execution is not permitted\n\nDuring runtime, the UART protocol is used to start a read of address 0x10000000, 0x280C0000, which both lay in regions, that allow read access and address 0x28100000, which lays in a restricted address range. A read in that restricted address range causes an exception, which can only be recovered by a hardware reset.\n\n**STDOUT setting**\n\nInitialization of the GPIO for UART is done in the \u003ca href=\"https://infineon.github.io/retarget-io/html/group__group__board__libs.html#ga21265301bf6e9239845227c2aead9293\"\u003e\u003ci\u003ecy_retarget_io_init()\u003c/i\u003e\u003c/a\u003e function.\n- Initialize the pin specified by CYBSP_DEBUG_UART_TX as UART TX, the pin specified by CYBSP_DEBUG_UART_RX as UART RX (these pins are connected to KitProg3 COM port)\n- The serial port parameters become to 8N1 and 115200 baud\n\n**MPU setting**\n\n- To setup the MPU, \u003ca href=\"https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__prot__functions__mpu.html#ga8b368e9846d5a3b8cd284131562376b1\"\u003e\u003ci\u003eCy_Prot_ConfigMpuStruct()\u003c/i\u003e\u003c/a\u003e is called with using structure \u003ca href=\"https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/structcy__stc__mpu__cfg__t.html\"\u003e\u003ci\u003ecy_stc_mpu_cfg_t\u003c/i\u003e\u003c/a\u003e as argument\n\n- The MPU is enabled by  \u003ca href=\"https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__prot__functions__mpu.html#gaf86849b6ef266090238dc4f5d59161f2\"\u003e\u003ci\u003eCy_Prot_EnableMpuStruct()\u003c/i\u003e\u003c/a\u003e.\n\n**Fault handling**\n\nThe fault handler \u003ca href=\"https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syslib__functions.html#ga0852597c5a10b76413a7063711043fef\"\u003e\u003ci\u003eCy_SysLib_ProcessingFault()\u003c/i\u003e\u003c/a\u003e is overwritten to display MMFAR and MMFSR on read exception.\n\n## Run and Test\nFor this example, a terminal emulator is required for displaying outputs. Install a terminal emulator if you do not have one. Instructions in this document use [Tera Term](https://teratermproject.github.io/index-en.html).\n\nAfter code compilation, perform the following steps to flashing the device:\n1. Connect the board to your PC using the provided USB cable through the KitProg3 USB connector.\n2. Open a terminal program and select the KitProg3 COM port. Set the serial port parameters to 8N1 and 115200 baud.\n3. Program the board using one of the following:\n    - Select the code example project in the Project Explorer.\n    - In the **Quick Panel**, scroll down, and click **[Project Name] Program (KitProg3_MiniProg4)**.\n4. After programming, the code example starts automatically. Confirm that the messages are displayed on the UART terminal.\n\n    - *Terminal output on program startup*\u003cBR\u003e\u003cimg src=\"./images/terminal.gif\" width=\"640\" /\u003e\n\n5. Pressing 1 or 2 will return the data of the specified regions. By pressing 3, a read access to a protected region is created and causes the MPU to raise an exception.\n\n    - *Terminal output on memory read*\u003cBR\u003e\u003cimg src=\"./images/read.gif\" width=\"640\" /\u003e\n\n6. You can debug the example to step through the code. In the IDE, use the **[Project Name] Debug (KitProg3_MiniProg4)** configuration in the **Quick Panel**. For details, see the \"Program and debug\" section in the [Eclipse IDE for ModusToolbox™ software user guide](https://www.infineon.com/dgdl/?fileId=8ac78c8c8929aa4d0189bd07dd6113f9).\n\n**Note:** **(Only while debugging)** On the CM7 CPU, some code in *main()* may execute before the debugger halts at the beginning of *main()*. This means that some code executes twice: once before the debugger stops execution, and again after the debugger resets the program counter to the beginning of *main()*. See [KBA231071](https://community.infineon.com/t5/Knowledge-Base-Articles/PSoC-6-MCU-Code-in-main-executes-before-the-debugger-halts-at-the-first-line-of/ta-p/253856) to learn about this and for the workaround.\n\n## References  \n\nRelevant Application notes are:\n- [AN235305](https://www.infineon.com/dgdl/?fileId=8ac78c8c8b6555fe018c1fddd8a72801) - Getting started with TRAVEO\u0026trade; T2G family MCUs in ModusToolbox\u0026trade;\n- [AN219843](https://www.infineon.com/dgdl/?fileId=8ac78c8c7cdc391c017d0d3abf4b6772) - Protection Configuration in TRAVEO™ T2G MCU\n\nModusToolbox™ is available online:\n- \u003chttps://www.infineon.com/modustoolbox\u003e\n\nAssociated TRAVEO™ T2G MCUs can be found on:\n- \u003chttps://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cortex-microcontroller/\u003e\n\nMore code examples can be found on the GIT repository:\n- [TRAVEO™ T2G Code examples](https://github.com/orgs/Infineon/repositories?q=mtb-t2g-\u0026type=all\u0026language=\u0026sort=)\n\nFor additional trainings, visit our webpage:  \n- [TRAVEO™ T2G trainings](https://www.infineon.com/cms/en/product/microcontroller/32-bit-traveo-t2g-arm-cortex-microcontroller/32-bit-traveo-t2g-arm-cortex-for-cluster/traveo-t2g-cyt4dn/#!trainings)\n\nFor questions and support, use the TRAVEO™ T2G Forum:  \n- \u003chttps://community.infineon.com/t5/TRAVEO-T2G/bd-p/TraveoII\u003e  \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Finfineon%2Fmtb-t2g-example-cpu-mpu-configuration","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Finfineon%2Fmtb-t2g-example-cpu-mpu-configuration","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Finfineon%2Fmtb-t2g-example-cpu-mpu-configuration/lists"}