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align=\"center\"\u003e\n  \u003cimg alt=\"ROHD\" src=\"https://intel.github.io/rohd-website/assets/images/rohd_logo_w_white_background.svg\"\u003e\n\u003c/p\u003e\n\n# Rapid Open Hardware Development (ROHD) Framework\n\n[![Tests](https://github.com/intel/rohd/actions/workflows/general.yml/badge.svg?event=push)](https://github.com/intel/rohd/actions/workflows/general.yml)\n[![API Docs](https://img.shields.io/badge/API%20Docs-generated-success)](https://intel.github.io/rohd/rohd/rohd-library.html)\n[![Chat](https://img.shields.io/discord/1001179329411166267?label=Chat)](https://discord.gg/jubxF84yGw)\n[![License](https://img.shields.io/badge/License-BSD--3-blue)](https://github.com/intel/rohd/blob/main/LICENSE)\n[![Contributor Covenant](https://img.shields.io/badge/Contributor%20Covenant-2.1-4baaaa.svg)](https://github.com/intel/rohd/blob/main/CODE_OF_CONDUCT.md)\n\nROHD (pronounced like \"road\") is a framework for describing and verifying hardware in the Dart programming language.\n\n## Documentation\n\nFor documentation, guides, and more, [**visit the ROHD Website!**](https://intel.github.io/rohd-website/)\n\n- [Install now](https://intel.github.io/rohd-website/get-started/overview/)\n- [Try it in-browser](https://dartpad.dev/?id=375e800a9d0bd402c9bfa5ebe2210c40)\n- [User Guide](https://intel.github.io/rohd-website/docs/sample-example/)\n- [Tutorials](https://github.com/intel/rohd/tree/main/doc/tutorials)\n- [YouTube Channel](https://www.youtube.com/@ROHD-DEV)\n- [API Docs](https://intel.github.io/rohd/rohd/rohd-library.html)\n- [Blog](https://intel.github.io/rohd-website/blog/)\n- [Contributing](https://github.com/intel/rohd/blob/main/CONTRIBUTING.md)\n\nYou can also open this repository in a GitHub Codespace to run the example in your browser with a full IDE.  This is also an easy way to get started with contributions!\n\n  [![Open in GitHub Codespaces](https://github.com/codespaces/badge.svg)](https://github.com/codespaces/new?hide_repo_select=true\u0026ref=main\u0026repo=409325108)\n\n### Get involved\n\n- [Join the Discord chat](https://discord.gg/jubxF84yGw)\n- [Attend the ROHD Forum meetings](https://intel.github.io/rohd-website/forum/rohd-forum/)\n- [GitHub Discussions](https://github.com/intel/rohd/discussions)\n\n## About ROHD\n\n- Full power of the modern **Dart language** for hardware design and verification\n- Makes **validation collateral** simpler to develop and debug.  The [ROHD Verification Framework](https://github.com/intel/rohd-vf) helps build well-structured testbenches.\n- Develop **layers of abstraction** within a hardware design, making it more flexible and powerful\n- Easy **IP integration** and **interfaces**; using an IP is as easy as an import.  Reduces tedious, redundant, and error prone aspects of integration\n- **Simple and fast build**, free of complex build systems and EDA vendor tools\n- Can use the excellent pub.dev **package manager** and all the packages it has to offer\n- Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform dumper** to .vcd file format\n- Conversion of modules to equivalent, human-readable, structurally similar **SystemVerilog** for integration or downstream tool consumption\n- **Run-time dynamic** module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents\n- Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components.\n- Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.\n- Excellent, simple, fast **unit-testing** framework\n- **Less verbose** than alternatives (fewer lines of code)\n- Enables **higher quality** development\n- Replaces hacky perl/python scripting for automation with powerful **native control of design generation**\n- Fewer bugs and lines of code means **shorter development schedule**\n- Support for **cosimulation with verilog modules** (via [ROHD Cosim](https://github.com/intel/rohd-cosim)) and **instantiation of verilog modules** in generated SystemVerilog code\n- Use **modern IDEs** like Visual Studio Code, with excellent static analysis, fast autocomplete, built-in debugger, linting, git integration, extensions, and much more\n- Simulate with **various abstraction levels of models** from architectural, to functional, to cycle-accurate, to RTL levels in the same language and environment.\n\nROHD is *not* a new language, it is *not* a hardware description language (HDL), and it is *not* a version of High-Level Synthesis (HLS).  ROHD can be classified as a generator framework.\n\nYou can think of this project as an attempt to *replace* SystemVerilog and related build systems as the front-end methodology of choice in the industry.\n\nOne of ROHD's goals is to help grow an open-source community around reusable hardware designs and verification components.\n\n## Contributing\n\nROHD is under active development.  If you're interested in contributing, have feedback or a question, or found a bug, please see [CONTRIBUTING.md](https://github.com/intel/rohd/blob/main/CONTRIBUTING.md).\n\n----------------\n\nCopyright (C) 2021-2025 Intel Corporation  \nSPDX-License-Identifier: BSD-3-Clause\n","funding_links":[],"categories":["Meta HDL and Transpilers","Dart","Circuit Compilers","Frameworks:","Other Frameworks"],"sub_categories":["ROHD Verification Framework"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fintel%2Frohd","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fintel%2Frohd","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fintel%2Frohd/lists"}