{"id":13775007,"url":"https://github.com/intel/rohd-cosim","last_synced_at":"2026-02-19T09:33:36.536Z","repository":{"id":65852362,"uuid":"596776272","full_name":"intel/rohd-cosim","owner":"intel","description":"Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators","archived":false,"fork":false,"pushed_at":"2025-06-17T21:52:04.000Z","size":891,"stargazers_count":24,"open_issues_count":23,"forks_count":5,"subscribers_count":2,"default_branch":"main","last_synced_at":"2025-10-22T23:02:19.911Z","etag":null,"topics":["co-simulation","cocotb","cosim","cosimulation","dart","framework","hardware","hardware-design","hardware-verification","python","rohd","rohd-vf","rtl","simulator"],"latest_commit_sha":null,"homepage":"https://pub.dev/packages/rohd_cosim","language":"Dart","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"bsd-3-clause","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/intel.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":"CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":"SECURITY.md","support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2023-02-02T22:38:58.000Z","updated_at":"2025-08-21T22:59:41.000Z","dependencies_parsed_at":"2024-01-07T01:17:25.313Z","dependency_job_id":"4001ac91-2137-43ed-8ede-54c317ad7607","html_url":"https://github.com/intel/rohd-cosim","commit_stats":null,"previous_names":[],"tags_count":3,"template":false,"template_full_name":null,"purl":"pkg:github/intel/rohd-cosim","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/intel%2Frohd-cosim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/intel%2Frohd-cosim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/intel%2Frohd-cosim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/intel%2Frohd-cosim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/intel","download_url":"https://codeload.github.com/intel/rohd-cosim/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/intel%2Frohd-cosim/sbom","scorecard":{"id":490842,"data":{"date":"2025-08-11","repo":{"name":"github.com/intel/rohd-cosim","commit":"31900d95ab7fb6a31b5fe7f2ad80939334b41592"},"scorecard":{"version":"v5.2.1-40-gf6ed084d","commit":"f6ed084d17c9236477efd66e5b258b9d4cc7b389"},"score":5.5,"checks":[{"name":"Code-Review","score":0,"reason":"Found 0/25 approved changesets -- score normalized to 0","details":null,"documentation":{"short":"Determines if the project requires human code review before pull requests (aka merge requests) are merged.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#code-review"}},{"name":"Security-Policy","score":10,"reason":"security policy file detected","details":["Info: security policy file detected: SECURITY.md:1","Info: Found linked content: SECURITY.md:1","Info: Found disclosure, vulnerability, and/or timelines in security policy: SECURITY.md:1","Info: Found text in security policy: SECURITY.md:1"],"documentation":{"short":"Determines if the project has published a security policy.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#security-policy"}},{"name":"Dangerous-Workflow","score":10,"reason":"no dangerous workflow patterns detected","details":null,"documentation":{"short":"Determines if the project's GitHub Action workflows avoid dangerous patterns.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#dangerous-workflow"}},{"name":"Token-Permissions","score":10,"reason":"GitHub workflow tokens follow principle of least privilege","details":["Warn: jobLevel 'contents' permission set to 'write': .github/workflows/general.yml:84","Info: found token with 'none' permissions: .github/workflows/general.yml:1","Info: found token with 'none' permissions: .github/workflows/general.yml:1"],"documentation":{"short":"Determines if the project's workflows follow the principle of least privilege.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#token-permissions"}},{"name":"Maintained","score":1,"reason":"2 commit(s) and 0 issue activity found in the last 90 days -- score normalized to 1","details":null,"documentation":{"short":"Determines if the project is \"actively maintained\".","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#maintained"}},{"name":"Binary-Artifacts","score":10,"reason":"no binaries found in the repo","details":null,"documentation":{"short":"Determines if the project has generated executable (binary) artifacts in the source repository.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#binary-artifacts"}},{"name":"CII-Best-Practices","score":0,"reason":"no effort to earn an OpenSSF best practices badge detected","details":null,"documentation":{"short":"Determines if the project has an OpenSSF (formerly CII) Best Practices Badge.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#cii-best-practices"}},{"name":"Packaging","score":-1,"reason":"packaging workflow not detected","details":["Warn: no GitHub/GitLab publishing workflow detected."],"documentation":{"short":"Determines if the project is published as a package that others can easily download, install, easily update, and uninstall.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#packaging"}},{"name":"Fuzzing","score":0,"reason":"project is not fuzzed","details":["Warn: no fuzzer integrations found"],"documentation":{"short":"Determines if the project uses fuzzing.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#fuzzing"}},{"name":"License","score":10,"reason":"license file detected","details":["Info: project has a license file: LICENSE:0","Info: FSF or OSI recognized license: BSD 3-Clause \"New\" or \"Revised\" License: LICENSE:0"],"documentation":{"short":"Determines if the project has defined a license.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#license"}},{"name":"Signed-Releases","score":-1,"reason":"no releases found","details":null,"documentation":{"short":"Determines if the project cryptographically signs release artifacts.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#signed-releases"}},{"name":"Pinned-Dependencies","score":0,"reason":"dependency not pinned by hash detected -- score normalized to 0","details":["Warn: GitHub-owned GitHubAction not pinned by hash: .github/workflows/general.yml:21: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: third-party GitHubAction not pinned by hash: .github/workflows/general.yml:24: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: third-party GitHubAction not pinned by hash: .github/workflows/general.yml:29: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: third-party GitHubAction not pinned by hash: .github/workflows/general.yml:35: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: GitHub-owned GitHubAction not pinned by hash: .github/workflows/general.yml:56: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: third-party GitHubAction not pinned by hash: .github/workflows/general.yml:75: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: GitHub-owned GitHubAction not pinned by hash: .github/workflows/general.yml:89: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: third-party GitHubAction not pinned by hash: .github/workflows/general.yml:92: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: third-party GitHubAction not pinned by hash: .github/workflows/general.yml:101: update your workflow using https://app.stepsecurity.io/secureworkflow/intel/rohd-cosim/general.yml/main?enable=pin","Warn: pipCommand not pinned by hash: tool/gh_actions/install_python_dependencies.sh:14","Info:   0 out of   3 GitHub-owned GitHubAction dependencies pinned","Info:   0 out of   6 third-party GitHubAction dependencies pinned","Info:   0 out of   1 pipCommand dependencies pinned"],"documentation":{"short":"Determines if the project has declared and pinned the dependencies of its build process.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#pinned-dependencies"}},{"name":"Branch-Protection","score":-1,"reason":"internal error: error during branchesHandler.setup: internal error: githubv4.Query: Resource not accessible by integration","details":null,"documentation":{"short":"Determines if the default and release branches are protected with GitHub's branch protection settings.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#branch-protection"}},{"name":"Vulnerabilities","score":9,"reason":"1 existing vulnerabilities detected","details":["Warn: Project is vulnerable to: PYSEC-2024-48 / GHSA-fj7x-q9j7-g6q6"],"documentation":{"short":"Determines if the project has open, known unfixed vulnerabilities.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#vulnerabilities"}},{"name":"SAST","score":0,"reason":"SAST tool is not run on all commits -- score normalized to 0","details":["Warn: 0 commits out of 20 are checked with a SAST tool"],"documentation":{"short":"Determines if the project uses static code analysis.","url":"https://github.com/ossf/scorecard/blob/f6ed084d17c9236477efd66e5b258b9d4cc7b389/docs/checks.md#sast"}}]},"last_synced_at":"2025-08-19T19:05:41.996Z","repository_id":65852362,"created_at":"2025-08-19T19:05:41.996Z","updated_at":"2025-08-19T19:05:41.996Z"},"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29609524,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-02-19T06:47:36.664Z","status":"ssl_error","status_checked_at":"2026-02-19T06:45:47.551Z","response_time":117,"last_error":"SSL_connect returned=1 errno=0 peeraddr=140.82.121.5:443 state=error: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["co-simulation","cocotb","cosim","cosimulation","dart","framework","hardware","hardware-design","hardware-verification","python","rohd","rohd-vf","rtl","simulator"],"created_at":"2024-08-03T17:01:32.692Z","updated_at":"2026-02-19T09:33:36.520Z","avatar_url":"https://github.com/intel.png","language":"Dart","funding_links":[],"categories":["Verification Frameworks"],"sub_categories":[],"readme":"[![Open in GitHub Codespaces](https://github.com/codespaces/badge.svg)](https://github.com/codespaces/new?hide_repo_select=true\u0026ref=main\u0026repo=596776272)\n\n[![Tests](https://github.com/intel/rohd-cosim/actions/workflows/general.yml/badge.svg?event=push)](https://github.com/intel/rohd-cosim/actions/workflows/general.yml)\n[![API Docs](https://img.shields.io/badge/API%20Docs-generated-success)](https://intel.github.io/rohd-cosim/rohd_cosim/rohd_cosim-library.html)\n[![Chat](https://img.shields.io/discord/1001179329411166267?label=Chat)](https://discord.gg/jubxF84yGw)\n[![License](https://img.shields.io/badge/License-BSD--3-blue)](https://github.com/intel/rohd-cosim/blob/main/LICENSE)\n[![Contributor Covenant](https://img.shields.io/badge/Contributor%20Covenant-2.1-4baaaa.svg)](https://github.com/intel/rohd-cosim/blob/main/CODE_OF_CONDUCT.md)\n\n# ROHD Cosim\n\nROHD Framework Co-simulation (ROHD Cosim) is a Dart package built upon the [Rapid Open Hardware Development (ROHD) framework](https://github.com/intel/rohd) for cosimulation between the ROHD Simulator and a SystemVerilog simulator.\n\nCommon use cases include:\n\n- Instantiating a SystemVerilog module within a ROHD Module and running a simulation.\n- Using ROHD and the [ROHD Verification Framework (ROHD-VF)](https://github.com/intel/rohd-vf) to build a testbench for a SystemVerilog module.\n- Connecting and simulating a ROHD and ROHD-VF developed functional model to a empty shell located within a SystemVerilog hierarchy.\n- Developing a mixed-simulation model where portions of design and/or testbench are in ROHD/ROHD-VF and other are in SystemVerilog or other languages which can run in or interact with a SystemVerilog simulator.\n\nWhen you instantiate a SystemVerilog module within the ROHD simulator with ROHD Cosim, from the perspective of the rest of the ROHD environment it looks just like any other ROHD module.  You can run simulations, set breakpoints and debug, etc. even with the SystemVerilog simulator running in cosimulation.\n\n## Prerequisites\n\nROHD Cosim relies on a python package called [cocotb](https://docs.cocotb.org/en/stable/) and its GPI library for communicating to SystemVerilog simulators.  The cocotb libraries have good support for a variety of simulators and have been used by many silicon and FPGA projects.\n\nDetailed instructions for installing cocotb are available here: \u003chttps://docs.cocotb.org/en/stable/install.html\u003e.  The instructions generally boil down to:\n\n```shell\npip install cocotb\n```\n\nYou will also need your favorite SystemVerilog simulator to do cosimulation between ROHD and SystemVerilog modules.  ROHD Cosim does *not* do any SystemVerilog parsing or SystemVerilog simulation itself.\n\nSee the section on [support and limitations](#support--limitations) for more details on simulators, versions, limitations, etc.\n\n## Using ROHD Cosim\n\nThere are two steps to using ROHD Cosim:\n\n### 1. Wrap your SystemVerilog module\n\nWrap your SystemVerilog module with ROHD's [`ExternalSystemVerilogModule`](https://intel.github.io/rohd/rohd/ExternalSystemVerilogModule-class.html) and apply the `Cosim` mixin.\n\nFor example, here are corresponding SystemVerilog module definitions and a wrapper for it with Cosim.\n\n```verilog\n// example_cosim_module.v\nmodule my_cosim_test_module(\n    input logic a,\n    input logic b,\n    output logic a_bar,\n    output logic b_same,\n    output logic c_none\n);\n\nassign a_bar = ~a;\nassign b_same = b;\nassign c_none = 0;\n\nendmodule\n```\n\n```dart\n// example_cosim_module.dart\nclass ExampleCosimModule extends ExternalSystemVerilogModule with Cosim {\n  Logic get aBar =\u003e output('a_bar');\n  Logic get bSame =\u003e output('b_same');\n\n  @override\n  List\u003cString\u003e get verilogSources =\u003e ['./example_cosim_module.v'];\n\n  ExampleCosimModule(Logic a, Logic b, {String name = 'ecm'})\n      : super(definitionName: 'my_cosim_test_module', name: name) {\n    addInput('a', a);\n    addInput('b', b);\n    addOutput('a_bar');\n    addOutput('b_same');\n    addOutput('c_none');\n  }\n}\n```\n\nYou can add inputs and output using any mechanism, including ROHD [`Interface`](https://intel.github.io/rohd/rohd/Interface-class.html)s.\n\n### 2. Generate a connector and start the cosimulation\n\nCall the `Cosim.connectToSimulation` function with an appropriate configuration after `Module.build` to connect to the SystemVerilog simulator.\n\n### Additional information\n\n- Note that for cosimulation to execute, the ROHD `Simulator` must be running.\n- Note that with the cosimulation process running in a unit test suite, you have an additional thing to reset each `tearDown`: `Cosim.reset()`.\n- The `example/` directory has a counter example similar to what's available in the ROHD and ROHD-VF examples.\n- The ROHD Cosim test suite in `test/` is a good reference for some examples of how to set things up.\n\n## Cosimulation Configurations\n\nThere are three different types of configuration that can be used when connecting to the SystemVerilog simulation: \"wrap\", \"custom\", and \"port\".\n\n### Wrap Configuration\n\nThe wrap configuration is the simplest way to get started with cosimulation if you don't already have an existing build and simulation system set up for the SystemVerilog module.\n\nPass a `CosimWrapConfig` object into the `Cosim.connectToSimulation` call with information about which simulator you want to use and let ROHD Cosim take care of the rest!  It will automatically create a wrapper with all SystemVerilog submodules for each that needs to be cosimulated.\n\nThe below diagram shows how the wrap configuration connects to your simulation.  ROHD will generate a Makefile and connector for your design, and then connect to it by listening to some port information coming through stdout from the simulation process.\n\n![Wrap Config Diagram](https://github.com/intel/rohd-cosim/raw/main/doc/diagrams/wrap.png)\n\nThe example in `example/main.dart` uses the wrap configuration and is a good reference to get started.\n\n### Custom Configuration\n\nA custom configuration is a good approach if you already have a build system set up for your design and want to make the minimum changes possible.\n\nPass a `CosimCustomConfig` object into the `Cosim.connectToSimulation` call with information about how to launch the simulation and it will handle the rest.\n\nROHD Cosim will generate a cocotb-based python connector which is launched by the simulation process.\n\nROHD Cosim communicates with the python connector through a local socket.  ROHD watches for a special string with port information that comes from stdout via the python connector for how to connect.  If you mask `stdout` (e.g. to some other file), you need to find another way to pass that information through.\n\nYour SystemVerilog build will need to be configured to properly integrate the cocotb libraries.  You can follow these instructions for your choice of simulator: \u003chttps://docs.cocotb.org/en/stable/custom_flows.html\u003e\n\nYou will need to set some environment variables during simulation so that cocotb can determine what to run:\n\n```shell\n# Modules to search for test functions (should match python file name and module path generated by ROHD Cosim)\nexport MODULE=cosim_test_module\n \nexport TOPLEVEL_LANG=verilog\n \n# TOPLEVEL is the name of the toplevel module in your Verilog build\nexport TOPLEVEL=top_tb\n```\n\nYou will also need to ensure the following plusarg is passed to your simulation:\n\n```shell\n+define+COCOTB_SIM=1\n```\n\nThe diagram below shows how the custom configuration connects to your simulation.  Your custom build flow generates the simulation executable, and then ROHD cosim takes care of the rest similar to the wrap configuration.\n\n![Custom Config Diagram](https://github.com/intel/rohd-cosim/raw/main/doc/diagrams/custom.png)\n\n### Port Configuration\n\nA port configuration is an even more specialized config in case you have not only your own custom build system, but a custom simulation run system as well.  With the port configuration, you create a `PortConfig` object to the `Cosim.connectToSimulation` call with information about what unix socket port it should connect to.  In this way, it is no longer necessary for ROHD Cosim to be the launcher of the SystemVerilog simulation: another process can launch the simulation and then ROHD Cosim can attach at the specified port.\n\nTo build this system may require some custom python code to manually pass the port information where it needs to go.  The file `python/rohd_port_connector.py` can help with a lot of this.\n\nCheck out `test/port_test.dart` for a good example of how to make this work.\n\nThe diagram below shows how the port configuration connects to your simulation.  Your custom build flow generates the simulation executable, and your custom run flow starts the simulation.  You must create some mechanism, such as through a custom cocotb test, to pass port information back to ROHD cosim.  In this diagram, the custom test is launching the actual ROHD process with a port argument on the command line.\n\n![Port Config Diagram](https://github.com/intel/rohd-cosim/raw/main/doc/diagrams/port.png)\n\n## Support \u0026 Limitations\n\nROHD Cosim depends on cross-compatibility with SystemVerilog simulators and the libraries from cocotb that enable VPI-based communication between them. Because of this, there are some limitations which may be version and simulator specific, as well as some fundamental limitations that have to do with the communication mechanisms.\n\n- The simulation must occur over time.  That is, it is not possible to have a \"purely combinational\" block of logic, change an input, and view an instantaneous output change, as you normally can with ROHD modules.  This is because coordination between the ROHD simulation and the SystemVerilog simulator is coordinated by `Simulator` phasing.  Therefore, changes on the output of a SystemVerilog cosimulated module will not update until some time has passed.\n- ROHD Cosim can support simulators supported by cocotb, but has only been tested with those officially listed in the [`SystemVerilogSimulator` enum](https://intel.github.io/rohd-cosim/rohd_cosim/SystemVerilogSimulator.html).\n- Cross-version compatibility between ROHD Cosim, cocotb, and SystemVerilog simulators can, unfortunatley, be delicate.  Check the [simulator support documentation from cocotb](https://docs.cocotb.org/en/stable/simulator_support.html) for more details about which versions of which simulators will work well with which versions of cocotb (and thus ROHD Cosim).\n- Different SystemVerilog simulators have different limitations and capabilities, and thus those features would be limited in cosimulation as well. For example, Verilator does not support X/Z values.\n- In/Out ports and bidirectional wires are supported in ROHD Cosim, as they are in ROHD, however contention may not be calculated at these port boundaries in a realistic way. This has to do with how ROHD Cosim sends and receives updates with the SystemVerilog simulator. If the SystemVerilog simulator resolves a value or contention on an inout port, it may not be possible for ROHD to determine whether the contention can/should break, for example.\n\n----------------\n2022 September 9  \nAuthor: Max Korbel \u003c\u003cmax.korbel@intel.com\u003e\u003e\n\nCopyright (C) 2022-2025 Intel Corporation  \nSPDX-License-Identifier: BSD-3-Clause\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fintel%2Frohd-cosim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fintel%2Frohd-cosim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fintel%2Frohd-cosim/lists"}