{"id":25211714,"url":"https://github.com/jack74387/single-cycle-8-bit-cpu","last_synced_at":"2026-02-26T02:46:13.759Z","repository":{"id":276644727,"uuid":"929857058","full_name":"jack74387/Single-Cycle-8-bit-CPU","owner":"jack74387","description":"Single-Cycle 8-bit CPU designed for basic instruction execution with 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Single-Cycle-8-bit-CPU\nThis repository contains the design and implementation of a single-cycle 8-bit processor with only two registers, developed as part of the course project.\n\n## Instruction Set Architecture (ISA)\n\nThe processor follows a simple instruction encoding scheme where the operation can be identified by examining the top bits of each byte.\n\n### Key Features\n- **Separate instruction and data memory**\n- **Two general-purpose registers (`$ra`, `$rb`)**\n- Supports arithmetic, logical, and branching instructions.\n\n### Instruction Encoding Table\n\u003ctable border=\"1\" cellspacing=\"0\" cellpadding=\"5\" style=\"border-color: rgb(239, 239, 239);\"\u003e\n  \u003ctr\u003e\n    \u003cth\u003eBit\u003c/th\u003e\n    \u003cth\u003e7\u003c/th\u003e\n    \u003cth\u003e6\u003c/th\u003e\n    \u003cth\u003e5\u003c/th\u003e\n    \u003cth\u003e4\u003c/th\u003e\n    \u003cth\u003e3\u003c/th\u003e\n    \u003cth\u003e2\u003c/th\u003e\n    \u003cth\u003e1\u003c/th\u003e\n    \u003cth\u003e0\u003c/th\u003e\n    \u003cth\u003eDescription\u003c/th\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003enop\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\n    \u003ctd\u003eNo operation\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003eand\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003erd\u003c/td\u003e\u003ctd\u003era\u003c/td\u003e\u003ctd\u003erb\u003c/td\u003e\n    \u003ctd\u003e$rd = $ra \u0026amp; $rb\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003eor\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003erd\u003c/td\u003e\u003ctd\u003era\u003c/td\u003e\u003ctd\u003erb\u003c/td\u003e\n    \u003ctd\u003e$rd = $ra | $rb\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003eadd\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003erd\u003c/td\u003e\u003ctd\u003era\u003c/td\u003e\u003ctd\u003erb\u003c/td\u003e\n    \u003ctd\u003e$rd = $ra + $rb\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003esub\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003erd\u003c/td\u003e\u003ctd\u003era\u003c/td\u003e\u003ctd\u003erb\u003c/td\u003e\n    \u003ctd\u003e$rd = $ra - $rb\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003elw\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003erd\u003c/td\u003e\u003ctd colspan=\"4\"\u003eimmediate\u003c/td\u003e\n    \u003ctd\u003e$rd = MEM[imm]\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003eori\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e0\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003erd\u003c/td\u003e\u003ctd colspan=\"4\"\u003eimmediate\u003c/td\u003e\n    \u003ctd\u003e$rd = $rd | imm\u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e\u003cb\u003ebeq\u003c/b\u003e\u003c/td\u003e\n    \u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd\u003e1\u003c/td\u003e\u003ctd colspan=\"5\"\u003eoffset\u003c/td\u003e\n    \u003ctd\u003eBranch if $ra == $rb\u003c/td\u003e\n  \u003c/tr\u003e\n\u003c/table\u003e\n\n---\n\n#### Notes\n- **nop:** No operation is performed.  \n- **Arithmetic operations:** Support basic logical and arithmetic functions (`and`, `or`, `add`, `sub`).  \n- **lw:** Loads data from memory into the register `$rd`.(**immediate uses un-signed extension**)     \n- **ori:** Bitwise OR between the register and immediate value.(**immediate uses un-signed extension**)   \n- **beq:** Branches to an offset if the two registers are equal.(**offset uses signed extension**)  \n\n### Branching Behavior\nThe `beq` instruction operates similarly to MIPS:\n```asm\nif $ra == $rb:\n  PC = PC + 1 + offset\nelse:\n  PC = PC + 1\n```\n---\n\n### CPU Circuit Diagram\n![CPU Circuit](./img/image.png)\n\n---\n\n### How to Build and Simulate\n- **Use Logisim to simulate this project:**  \n  1. Clone the repository:\n     ```bash\n     git clone https://github.com/jack74387/Single-Cycle-8-bit-CPU.git\n     ```\n  2. Open the circuit in **Logisim**:  \n     - download and install [Logisim](https://github.com/logisim-evolution/logisim-evolution?tab=readme-ov-file) \n     - Open `single-cycle-cpu.circ` from the project directory.  \n  3. Run the simulation:  \n     - Click the **Clock** icon to step through instructions manually.  \n     - Observe the changes in registers and memory for each cycle.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjack74387%2Fsingle-cycle-8-bit-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjack74387%2Fsingle-cycle-8-bit-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjack74387%2Fsingle-cycle-8-bit-cpu/lists"}