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Learning RISC-V\n\nThis project contains small programs and notes to help me learn [RISC-V](https://riscv.org/).\n\n## Register types\n\n| ABI Register | Description | Saver | ABI Register | Description | Saver |\n| --- | --- | --- | --- | --- | --- |\n| zero | Zero | immutable | ra | Return address | not applicable |\n| sp | Stack pointer | callee | gp | Global pointer | global |\n| tp | Thread pointer | global | t0-t2, t3-t6 | Temporary registers | none |\n| s0-s1, s2-s11 | Saved registers | callee | a0-a7 | Argument/return value | caller |\n\nReference: Table [Register Types](https://five-embeddev.com/quickref/regs_abi.html#register-types) on [Five EmbedDev](https://five-embeddev.com/).\n\n## Unix ABI (UABI)\n\n| Register | ABI Name | Description | Saver |\n| :--- | :--- | :--- | :--- |\n| x0 | zero | Hard-wired zero | — |\n| x1 | ra | Return address | caller |\n| x2 | sp | Stack pointer | callee |\n| x3 | gp | Global pointer | — |\n| x4 | tp | Thread pointer | — |\n| x5-7 | t0-2 | Temporaries | caller |\n| x8 | s0/fp | Saved register/frame pointer | callee |\n| x9 | s1 | Saved register | callee |\n| x10-11 | a0-1 | Function arguments/return values | caller |\n| x12-17 | a2-7 | Function arguments | caller |\n| x18-27 | s2-11 | Saved registers | callee |\n| x28-31 | t3-6 | Temporaries | caller |\n| f0-7 | ft0-7 | FP temporaries | caller |\n| f8-9 | fs0-1 | FP saved registers | callee |\n| f10-11 | fa0-1 | FP arguments/return values | caller |\n| f12-17 | fa2-7 | FP arguments | caller |\n| f18-27 | fs2-11 | FP saved registers | callee |\n| f28-31 | ft8-11 | FP temporaries | caller |\n\nReference: Table RISC-V calling convention register usage in chapter [Calling Convention](https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf).\n\n## Reference\n\n- [RISC-V Reference Card (PDF)](https://www.cl.cam.ac.uk/teaching/1516/ECAD+Arch/files/docs/RISCVGreenCardv8-20151013.pdf)\n- [RISC-V Instruction Set Specifications](https://msyksphinz-self.github.io/riscv-isadoc/html/index.html)\n- [RISC-V Linux syscall table](https://jborza.com/post/2021-05-11-riscv-linux-syscalls/)\n- [RISC-V Assembler: Arithmetic](https://projectf.io/posts/riscv-arithmetic/)\n- [RISC-V Add Immediate](https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html#addi)\n- [RISC-V Load Immediate](https://quantaly.github.io/riscv-li/)\n- [RISC-V Register Definitions](https://msyksphinz-self.github.io/riscv-isadoc/html/regs.html)\n- [Registers - RISC-V (WikiChip)](https://en.wikichip.org/wiki/risc-v/registers)\n- [What is the advantage of an x0 register?](https://www.reddit.com/r/RISCV/comments/qnacg2/what_is_the_advantage_of_an_x0_register/)\n- [List of standard RISC-V pseudoinstructions](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/riscv-asm.md#-a-listing-of-standard-risc-v-pseudoinstructions)\n- [RISC-V Instruction Set Manual](https://github.com/riscv/riscv-isa-manual)\n- [RISC-V ISA Specifications (Volume 1, Unprivileged Specification and Volume 2, Privileged Specification)](https://riscv.org/technical/specifications/)\n- [RISC-V ISA Manuals to HTML](https://five-embeddev.com/updates/2023/07/31/html-docs/)\n- [RISC-V Assembly Programmer's Manual](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/riscv-asm.md)\n- [Linux kernel system calls for all architectures](https://gpages.juszkiewicz.com.pl/syscalls-table/syscalls.html)\n- [Five EmbedDev: An Embedded RISC-V Blog](https://five-embeddev.com/)\n- [RiscV - Esercizi Base](https://chrisquack.medium.com/riscv-esercizi-base-a37c1830734a)\n- [Processor Design #2: Introduction to RISC-V](https://www.linkedin.com/pulse/processor-design-2-introduction-risc-v-simon-southwell/)\n- [RISC-V Reference (PDF)](https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_CARD.pdf)\n- [RISC-V Online Assembler](https://riscvasm.lucasteske.dev/)\n- [RISC-V System call table](https://jborza.com/post/2021-05-11-riscv-linux-syscalls/)\n- [The Magic of RISC-V Vector Processing (LaurieWired - YouTube)](https://youtu.be/Ozj_xU0rSyY?si=Ba6-AvblLUVcKzMW)\n- [Understanding RISC-V Calling Convention (PDF)](https://www2.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_CALL.pdf)\n- [Syscalls, exceptions, and\ninterrupts, …oh my! (PDF)](https://www.cs.cornell.edu/courses/cs3410/2019sp/schedule/slides/14-ecf-pre.pdf)\n- [LearnRISC-V - YouTube](https://www.youtube.com/@LearnRISCV/videos)\n- [RISC-V Directives](https://sourceware.org/binutils/docs/as/RISC_002dV_002dDirectives.html)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjackdbd%2Flearning-riscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjackdbd%2Flearning-riscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjackdbd%2Flearning-riscv/lists"}