{"id":30767965,"url":"https://github.com/jakubcabal/sdram-tester-fpga","last_synced_at":"2025-09-04T20:16:17.976Z","repository":{"id":99510249,"uuid":"306907071","full_name":"jakubcabal/sdram-tester-fpga","owner":"jakubcabal","description":"SDRAM Tester implemented in FPGA","archived":false,"fork":false,"pushed_at":"2021-05-01T09:32:28.000Z","size":62,"stargazers_count":7,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"main","last_synced_at":"2023-03-03T02:11:17.255Z","etag":null,"topics":["cyc1000","fpga","measures-throughput","python","sdram","sdram-controller","sdram-tester","vhdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jakubcabal.png","metadata":{},"created_at":"2020-10-24T14:57:54.000Z","updated_at":"2022-03-15T22:49:41.000Z","dependencies_parsed_at":"2023-09-09T20:33:02.749Z","dependency_job_id":null,"html_url":"https://github.com/jakubcabal/sdram-tester-fpga","commit_stats":null,"previous_names":[],"tags_count":null,"template":null,"template_full_name":null,"purl":"pkg:github/jakubcabal/sdram-tester-fpga","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jakubcabal%2Fsdram-tester-fpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jakubcabal%2Fsdram-tester-fpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jakubcabal%2Fsdram-tester-fpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jakubcabal%2Fsdram-tester-fpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jakubcabal","download_url":"https://codeload.github.com/jakubcabal/sdram-tester-fpga/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jakubcabal%2Fsdram-tester-fpga/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":273666323,"owners_count":25146351,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-09-04T02:00:08.968Z","response_time":61,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cyc1000","fpga","measures-throughput","python","sdram","sdram-controller","sdram-tester","vhdl"],"created_at":"2025-09-04T20:16:12.796Z","updated_at":"2025-09-04T20:16:17.960Z","avatar_url":"https://github.com/jakubcabal.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjakubcabal%2Fsdram-tester-fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjakubcabal%2Fsdram-tester-fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjakubcabal%2Fsdram-tester-fpga/lists"}