{"id":13958935,"url":"https://github.com/jasonlin316/RISC-V-CPU","last_synced_at":"2025-07-21T00:32:35.506Z","repository":{"id":138373744,"uuid":"186223687","full_name":"jasonlin316/RISC-V-CPU","owner":"jasonlin316","description":"A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.","archived":false,"fork":false,"pushed_at":"2019-12-02T17:08:52.000Z","size":21179,"stargazers_count":119,"open_issues_count":2,"forks_count":27,"subscribers_count":7,"default_branch":"master","last_synced_at":"2024-11-28T02:35:39.814Z","etag":null,"topics":["chip","gate-level","place-and-route","processor","risc-v","riscv32","tape-out","vector","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jasonlin316.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-05-12T07:14:07.000Z","updated_at":"2024-11-22T07:44:59.000Z","dependencies_parsed_at":null,"dependency_job_id":"b0663a4d-d89c-4ad4-af83-a318aef671a6","html_url":"https://github.com/jasonlin316/RISC-V-CPU","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/jasonlin316/RISC-V-CPU","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jasonlin316%2FRISC-V-CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jasonlin316%2FRISC-V-CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jasonlin316%2FRISC-V-CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jasonlin316%2FRISC-V-CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jasonlin316","download_url":"https://codeload.github.com/jasonlin316/RISC-V-CPU/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jasonlin316%2FRISC-V-CPU/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266221321,"owners_count":23894966,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["chip","gate-level","place-and-route","processor","risc-v","riscv32","tape-out","vector","verilog"],"created_at":"2024-08-08T13:02:07.419Z","updated_at":"2025-07-21T00:32:30.496Z","avatar_url":"https://github.com/jasonlin316.png","language":"Verilog","funding_links":[],"categories":["CPU RISC-V"],"sub_categories":["网络服务_其他"],"readme":null,"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjasonlin316%2FRISC-V-CPU","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjasonlin316%2FRISC-V-CPU","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjasonlin316%2FRISC-V-CPU/lists"}