{"id":22868961,"url":"https://github.com/jbilander/denise_to_fpga","last_synced_at":"2026-03-19T23:52:21.322Z","repository":{"id":193373698,"uuid":"680597935","full_name":"jbilander/Denise_to_FPGA","owner":"jbilander","description":"A small adapter-board that connects 12-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Denise to a FPGA-board via a 5V-tolerant buffer.","archived":false,"fork":false,"pushed_at":"2024-07-29T10:21:19.000Z","size":2926,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-06T16:04:55.920Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cc-by-sa-4.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jbilander.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-08-19T18:59:03.000Z","updated_at":"2024-08-20T04:06:12.000Z","dependencies_parsed_at":"2023-12-31T12:21:10.313Z","dependency_job_id":"1763b2ea-0571-4c8d-ab51-1a7c74c95d2f","html_url":"https://github.com/jbilander/Denise_to_FPGA","commit_stats":null,"previous_names":["jbilander/denise_to_fpga"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FDenise_to_FPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FDenise_to_FPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FDenise_to_FPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FDenise_to_FPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jbilander","download_url":"https://codeload.github.com/jbilander/Denise_to_FPGA/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246458002,"owners_count":20780677,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-13T12:44:42.933Z","updated_at":"2026-01-11T05:38:09.938Z","avatar_url":"https://github.com/jbilander.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# Denise_to_FPGA\nA small adapter-board that connects 12-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Denise to a FPGA-board via a 5V-tolerant buffer.\nA synchronous 14 MHz clock is generated from `C7M XOR CDAC` by using a `74LVC1G86`-chip. This will be fed into the FPGA's PLL.\n\nBoard is two layers.\n\nWORK IN PROGRESS, NOT FULLY TESTED YET!\n\n***\n\n\u003ca href=\"images/Denise_to_FPGA_pic1.png\"\u003e\n\u003cimg src=\"images/Denise_to_FPGA_pic1.png\" width=\"600\" height=\"306\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/Denise_to_FPGA_pic2.png\"\u003e\n\u003cimg src=\"images/Denise_to_FPGA_pic2.png\" width=\"600\" height=\"306\"\u003e\n\u003c/a\u003e\n\n***\n\u003ca href=\"images/Denise_to_FPGA_pic3.jpg\"\u003e\n\u003cimg src=\"images/Denise_to_FPGA_pic3.jpg\" width=\"384\" height=\"288\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/Denise_to_FPGA_pic4.jpg\"\u003e\n\u003cimg src=\"images/Denise_to_FPGA_pic4.jpg\" width=\"384\" height=\"288\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/Denise_to_FPGA_pic5.jpg\"\u003e\n\u003cimg src=\"images/Denise_to_FPGA_pic5.jpg\" width=\"384\" height=\"288\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/Denise_to_FPGA_pic6.jpg\"\u003e\n\u003cimg src=\"images/Denise_to_FPGA_pic6.jpg\" width=\"384\" height=\"288\"\u003e\n\u003c/a\u003e\n\n***\nBOM Rev. A\n---------\nDesignator  | Name/Value   | Package | Notes\n-|-|-|-|\nU1 | Voltage Regulator 3.3V, \u003cbr /\u003e LM1117-3.3 or \u003cbr /\u003e AMS1117-3.3 | SOT-223 | 3.3V 1A Low Drop-Out (LDO) [Voltage regulator](https://www.aliexpress.com/item/32869037691.html).\nU2,U3 | Bus Transceiver 74LVC245A  | TSSOP-20 | [74LVC245APW-T](https://www.mouser.com/ProductDetail/771-74LVC245APW-T)\nU4 | XOR Gate 74LVC1G86 | SOT-353 | [74LVC1G86](https://www.mouser.com/ProductDetail/621-74LVC1G86QSE-7)\nU5 | 48 pcs TH socket pins | 100 Pcs | IC Leads Receptacle, Length 9.7 mm gold or nickel plated.\u003cbr /\u003e[100 pcs](https://www.aliexpress.com/item/1005002830101899.html)\u003cbr /\u003e[300 pcs](https://www.aliexpress.com/item/1005004707554342.html)\u003cbr /\u003e[1000 pcs](https://www.aliexpress.com/item/32972142300.html)\u003cbr /\u003e[1000 pcs](https://www.aliexpress.com/item/32791545218.html)\nC1,C2 | Capacitor 10uF | 1206 | Caps for Voltage Regulator\nC3-C6 | Capacitor 0.1uF = 100nF | 0805 | Decoupling caps\nR1 | 22 or 33 Ω Resistor | 0805 | 22 or 33 Ω series resistor to [avoid reflections](https://embeddeddesignblog.blogspot.com/2022/07/why-do-we-need-series-resistor-on-clock.html) on the 14 MHz CLK\nJ1 | CDAC/CSYNC Two-Pin Header 2.54mm pitch | 2.54mm pitch | Connect a fly-lead here for old Rev. 3 A500 Motherboard that doesn't have these signals at the Denise socket. \nJ2 | VSYNC/HSYNC Two-Pin Header 2.54mm pitch | 2.54mm pitch | Connect a fly-lead here with connection to the Horizontal and Vertical sync on DB23-backside. \nJ3 | FPC connector, Right Angle, bottom contact | 0.5mm pitch, 40 positions | [TE Connectivity 4-1734592-0](https://www.mouser.com/ProductDetail/571-4-1734592-0) or [40p here](https://www.aliexpress.com/item/10000000478377.html)\n\n\n***\n\n[![CC BY-SA 4.0][cc-by-sa-shield]][cc-by-sa]\n\nThis work is licensed under a\n[Creative Commons Attribution-ShareAlike 4.0 International License][cc-by-sa].\n\n[![CC BY-SA 4.0][cc-by-sa-image]][cc-by-sa]\n\n[cc-by-sa]: http://creativecommons.org/licenses/by-sa/4.0/\n[cc-by-sa-image]: https://licensebuttons.net/l/by-sa/4.0/88x31.png\n[cc-by-sa-shield]: https://img.shields.io/badge/License-CC%20BY--SA%204.0-lightgrey.svg\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Fdenise_to_fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjbilander%2Fdenise_to_fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Fdenise_to_fpga/lists"}