{"id":22868971,"url":"https://github.com/jbilander/lisa_to_fpga","last_synced_at":"2026-01-08T10:56:36.987Z","repository":{"id":194497562,"uuid":"682245526","full_name":"jbilander/Lisa_to_FPGA","owner":"jbilander","description":"A small adapter-board that connects 24-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Lisa to a FPGA-board via a 5V-tolerant buffer.","archived":false,"fork":false,"pushed_at":"2024-07-29T09:56:41.000Z","size":2308,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-06T16:05:00.754Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cc-by-sa-4.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jbilander.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-08-23T18:53:53.000Z","updated_at":"2024-07-29T09:56:44.000Z","dependencies_parsed_at":null,"dependency_job_id":"2561cf75-b53e-4d81-9b8f-abb42c47d6ce","html_url":"https://github.com/jbilander/Lisa_to_FPGA","commit_stats":null,"previous_names":["jbilander/lisa_to_fpga"],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FLisa_to_FPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FLisa_to_FPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FLisa_to_FPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FLisa_to_FPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jbilander","download_url":"https://codeload.github.com/jbilander/Lisa_to_FPGA/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246458002,"owners_count":20780677,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-13T12:44:44.089Z","updated_at":"2026-01-08T10:56:36.950Z","avatar_url":"https://github.com/jbilander.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# Lisa_to_FPGA\nA small adapter-board that connects 24-bit RGB, 14 MHz CLK, PIXELSW and SYNC-signals on Lisa to a FPGA-board via a 5V-tolerant buffer.\n\nBoard is 37 x 55 mm 4-layers, hence should only be $2 for 5 PCBs at JLC.\n\nStackup:\u003cbr /\u003e\n* Signal/GND\n* GND\n* 3V3\n* Signal/GND\n\n\nWORK IN PROGRESS, NOT TESTED YET!\n\n***\n\n\u003ca href=\"images/Lisa_to_FPGA_A1200_pic1.png\"\u003e\n\u003cimg src=\"images/Lisa_to_FPGA_A1200_pic1.png\" width=\"600\" height=\"440\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/Lisa_to_FPGA_A1200_pic2.png\"\u003e\n\u003cimg src=\"images/Lisa_to_FPGA_A1200_pic2.png\" width=\"600\" height=\"440\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/Lisa_to_FPGA_A1200_pic3.png\"\u003e\n\u003cimg src=\"images/Lisa_to_FPGA_A1200_pic3.png\" width=\"600\" height=\"600\"\u003e\n\u003c/a\u003e\n\n***\n\nBOM Rev. A\n---------\nDesignator  | Name/Value   | Package | Notes\n-|-|-|-|\nU1 | Voltage Regulator 3.3V, \u003cbr /\u003e LM1117-3.3 or \u003cbr /\u003e AMS1117-3.3 | SOT-223 | 3.3V 1A Low Drop-Out (LDO) [Voltage regulator](https://www.aliexpress.com/item/32869037691.html).\nU2-U5 | Bus Transceiver 74LVC245A  | TSSOP-20 | [74LVC245APW-T](https://www.mouser.com/ProductDetail/771-74LVC245APW-T)\nU5 | PLCC-84 Through Hole Socket | PLCC-84 TH | [Preci-dip](https://www.mouser.com/ProductDetail/437-5408808424008)\u003cbr /\u003e[3M](https://www.mouser.com/ProductDetail/517-8484-11B1-RK-TP)\u003cbr /\u003e[Mill-Max](https://www.mouser.com/ProductDetail/575-948424)\u003cbr /\u003e[Adam-Tech](https://www.digikey.com/en/products/detail/adam-tech/PLCC-84-AT/9832990)\u003cbr /\u003e[A-CCS Tin](https://www.digikey.com/en/products/detail/assmann-wsw-components/A-CCS-084-Z-T/5023770)\u003cbr /\u003e[A-CCS Gold](https://www.digikey.com/en/products/detail/assmann-wsw-components/A-CCS-084-G-T/6674126)\u003cbr /\u003e[PLCC-84P DIP](https://www.aliexpress.com/item/1005002813417216.html)\nC1,C2 | Capacitor 10uF | 1206 | Caps for Voltage Regulator\nC3-C6 | Capacitor 0.1uF = 100nF | 0603 | Decoupling caps\nR1 | 22 or 33 Ω Resistor | 0805 | 22 or 33 Ω series resistor to [avoid reflections](https://embeddeddesignblog.blogspot.com/2022/07/why-do-we-need-series-resistor-on-clock.html) on the 14 MHz CLK\nJ1 | VSYNC/HSYNC/CSYNC Three-Pin Header 2.54mm pitch | 2.54mm pitch | Connect a fly-lead here with connection to the HS, VS and Csync leads on the DB23-backside. \nJ2 | FPC connector, Right Angle, bottom contact | 0.5mm pitch, 40 positions | [TE Connectivity 4-1734592-0](https://www.mouser.com/ProductDetail/571-4-1734592-0) or [40p here](https://www.aliexpress.com/item/10000000478377.html)\n\n***\n\n[![CC BY-SA 4.0][cc-by-sa-shield]][cc-by-sa]\n\nThis work is licensed under a\n[Creative Commons Attribution-ShareAlike 4.0 International License][cc-by-sa].\n\n[![CC BY-SA 4.0][cc-by-sa-image]][cc-by-sa]\n\n[cc-by-sa]: http://creativecommons.org/licenses/by-sa/4.0/\n[cc-by-sa-image]: https://licensebuttons.net/l/by-sa/4.0/88x31.png\n[cc-by-sa-shield]: https://img.shields.io/badge/License-CC%20BY--SA%204.0-lightgrey.svg\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Flisa_to_fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjbilander%2Flisa_to_fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Flisa_to_fpga/lists"}