{"id":22868979,"url":"https://github.com/jbilander/sf2000","last_synced_at":"2026-01-12T06:25:10.056Z","repository":{"id":81958914,"uuid":"443430153","full_name":"jbilander/SF2000","owner":"jbilander","description":"Spitfire 2000, A low-end 42 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 2000 co-pro slot (or A500 through an adapter).","archived":false,"fork":false,"pushed_at":"2025-01-27T17:38:18.000Z","size":30037,"stargazers_count":23,"open_issues_count":0,"forks_count":0,"subscribers_count":6,"default_branch":"main","last_synced_at":"2025-03-20T23:51:20.579Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cc-by-sa-4.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jbilander.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-12-31T21:48:55.000Z","updated_at":"2025-02-12T11:27:43.000Z","dependencies_parsed_at":"2024-12-13T12:44:52.194Z","dependency_job_id":"af645bac-cba7-447c-8be8-f79624f593f5","html_url":"https://github.com/jbilander/SF2000","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF2000","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF2000/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF2000/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF2000/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jbilander","download_url":"https://codeload.github.com/jbilander/SF2000/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246458009,"owners_count":20780678,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-13T12:44:45.566Z","updated_at":"2026-01-12T06:25:10.049Z","avatar_url":"https://github.com/jbilander.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# SF2000\nSpitfire 2000, A low-end 42 MHz Amiga Accelerator based on the Motorola 68SEC000 CPU\n\n***\n\nThis is WORK IN PROGRESS, a DIY hobby project. If you are going to make and sell boards you are also the one doing the customer support.\n\n***\n\nThe firmware for this board is in a separate repository available here: \u003cbr /\u003e\nhttps://github.com/jbilander/SF2000-FW\n\u003cbr /\u003e\n\n***\n\nRevision 1B\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic1.png\"\u003e\n\u003cimg src=\"images/SF2000_pic1.png\" width=\"360\" height=\"264\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic2.png\"\u003e\n\u003cimg src=\"images/SF2000_pic2.png\" width=\"360\" height=\"264\"\u003e\n\u003c/a\u003e\n\n***\n\n\u003ca href=\"images/SF2000_pic3.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic3.jpg\" width=\"360\" height=\"270\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic4.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic4.jpg\" width=\"360\" height=\"270\"\u003e\n\u003c/a\u003e\n\n***\n\nBOM Rev. 2B\n---------\nDesignator  | Name/Value   | Package | Notes\n-|-|-|-|\nU1 | Voltage Regulator 3.3V, \u003cbr /\u003e LM1117-3.3 or \u003cbr /\u003e AMS1117-3.3 | SOT-223 | 3.3V 1A Low Drop-Out (LDO) Linear Voltage regulator\nU2 | Voltage Regulator 4.3V, ABLIC S-1132B43-M5T1U or TPS73643DBVR | SOT-23-5 | 4.3V LDO Linear Voltage Regulator\u003cbr /\u003e[S-1132B43-M5T1U](https://www.digikey.com/en/products/detail/ablic-inc/S-1132B43-M5T1U/6112740)\nU3 | Voltage Regulator 1.2V, TLV73312PDBVR | SOT-23-5 | 1.2V LDO Linear Voltage Regulator\u003cbr /\u003e[TLV73312PDBVR](https://www.digikey.com/en/products/detail/texas-instruments/TLV73312PDBVR/5022371)\nU4,U5,U6 | Digital Bus Switch ICs 24-Bit FET, SN74CBT16211CDGGR or SN74CBT16811CDGGR | TSSOP-56 | FET Level-shifter \u003cbr /\u003e[SN74CBT16211CDGGR](https://www.digikey.com/en/products/detail/texas-instruments/SN74CBT16211CDGGR/864169) or \u003cbr /\u003e[SN74CBT16811CDGGR](https://www.digikey.com/en/products/detail/texas-instruments/sn74cbt16811cdggr/864186)\nU7 | Dual XOR gate SN74LVC2G86DCUR | VSSOP-8_2.3x2mm_P0.5mm | Generates 7 MHz CLK from ~(CCK XOR CCKQ) \u003cbr /\u003e[SN74LVC2G86DCUR](https://www.digikey.com/en/products/detail/texas-instruments/sn74lvc2g86dcur/484697)\nU8 | Efinix Trion T8 FPGA T8Q144C3 | LQFP-144_20x20mm_P0.5mm | FPGA - Field Programmable Gate Array, 7384 LE, 97 I/O \u003cbr /\u003e[T8Q144C3](https://www.digikey.com/en/products/detail/efinix-inc/t8q144c3/11591370)\nU9 | W25Q16JVSNIQ 16 Mbit SPI NOR Flash memory | SOIC-8_3.9x4.9mm_P1.27mm (150-mil Narrow JEDEC SOIC) | [W25Q16JVSNIQ](https://www.digikey.com/en/products/detail/winbond-electronics/w25q16jvsniq/6193768) or [AT25SF161B-SSHD-T](https://www.digikey.com/en/products/detail/renesas-electronics-corporation/AT25SF161B-SSHD-T/14549318)\nU10 | Motorola CPU MC68SEC000AA20 20MHz | QFP-64_14x14mm_Pitch0.8mm | [MC68SEC000AA20](https://shop.tvsat.com.pl/en_GB/searchquery/68sec000/1/phot/5?url=68sec000)\nU11 | SST39LF802C-55-4C-EKE or SST39LF800A-55-4C-EKE | TSOP-I-48_18.4x12mm_P0.5mm | NOR Flash 3.0 to 3.6V 8Mbit Multi-Purpose Flash (for Kickstart) \u003cbr /\u003e[S39LF802C554CEKE](https://www.mouser.com/ProductDetail/579-S39LF802C554CEKE)\u003cbr /\u003e[S39LF800A554CEKE](https://www.digikey.com/en/products/detail/microchip-technology/SST39LF800A-55-4C-EKE/2297824)\nU12 | 74AHCT14PW, Six Channel Schmitt Trigger Inverter | TSSOP-14_4.4x5mm_P0.65mm | [74AHCT14PW,118](https://www.digikey.com/en/products/detail/nexperia-usa-inc/74AHCT14PW-118/1229627) or \u003cbr /\u003e[SN74AHCT14PWR](https://www.digikey.com/en/products/detail/texas-instruments/SN74AHCT14PWR/276754)\nU13 | NOR Flash SST39LF040-55-4C-NHE-T | PLCC-32 | NOR Flash 3.0 to 3.6V \u003cbr /\u003e[SST39LF040554CN](https://www.digikey.com/en/products/detail/microchip-technology/sst39lf040-55-4c-nhe-t/4080132) \u003cbr /\u003e (or 39LF020, 39LF010)\nU14,U15 | SRAM ISSI IS61WV20488FBLL-10TLI  | TSOP-44 | First 4 MB SRAM \u003cbr /\u003eHigh-Speed, Async, 2Mbx8, 10ns, 2.4v-3.6v, 44 Pin TSOP II, RoHS \u003cbr /\u003e[IS61WV20488FBLL-10TLI](https://www.mouser.com/ProductDetail/870-61W20488FBLL10TI)\nU16,U17 | SRAM ISSI IS61WV20488FBLL-10TLI  | TSOP-44 | Second 4 MB (Optional) --\"-- \u003cbr /\u003e\nJ1 | Goldfingers on PCB | ENIG | Order PCB with Goldfingers, ENIG and 45 degrees chamfered edge (or chamfer the edge yourself with a file)\nJ2 | CFGIN-header Two-Pin Header | 2.54mm pitch | Put a Jumper shunt here to activate autoconfig, or a CONFIGOUT-wire from other device to the right (pin 2) in this header.  \nJ3 | JTAG-header   | Dual row 2.54mm (2 x 5) Pin Male Header | \nJ4 | JP-header JP2 | 2.00mm (2 x 1) Pin Male Header | Generate E-CLK (if internal 68k is removed from socket)\nJ5 | JP-header JP3 | 2.00mm (2 x 1) Pin Male Header | Rom overlay jumper\nJ6 | JP-header JP4 | 2.00mm (2 x 1) Pin Male Header | 4/8 MB SRAM Config\nJ7 | VCC/GND Two-Pin Header | 2.54mm pitch | VIN +5V \u003cbr /\u003e used when programming FPGA standalone (card not installed in the Amiga). Be careful with orientation, check polarity BEFORE plugging-in a phone charger or similar here.\nJ8 | Sunrom Micro SD Card Holder | 9-pin Micro SD card slot connector | [Sunrom Micro-SD card holder](https://www.aliexpress.com/item/32802051702.html)\nJ9 | SD_LED header, Two-Pin Header | 2.54mm pitch | Driven by U12 inverter buffer when /SD_CS is being asserted. Connect to here in order to drive an external HDD-LED\nJ10 | SD_ACTIVE low signal, Right angle Single-Pin Header | 0.64 mm square pin angled | Driven by U12 inverter buffer when /SD_CS is being asserted. Connect to here in order to drive a [LED-board](https://github.com/jbilander/A500_IDE_LED_board) (Active low +5V-signal)\nJ11 | Rom-bank selector | 2.00mm (2 x 1) Pin Male Header | Select first or second bank, address line A15 (pin 3) on U13 (SST39LF040)\nJ12 | CLOCKPORT-header | 2.00mm 22-Pin (2x11) Pin Male Header | Caution: This header is +5V levels. Be careful with orientation.\nJ13 | JP-header JP1 | 2.54mm (2 x 1) Pin Male Header | 7 MHz / Turbo selector\nX1 | Crystal Oscillator 20 MHz | Oscillator_7.0x5.0mm |\nR1 | 33 Ω Resistor | 0805 | Damping resistor for 20 MHz clock-signal coming from X1 oscillator\nR2 | 33 Ω Resistor | 0805 | Damping resistor for 7 MHz clock-signal coming from U7 (SN74LVC2G86DCUR)\nR3 | 33 Ω Resistor | 0805 | Damping resistor for CLKCPU clock-signal coming from FPGA pin 33\nR4 | ~220 Ω Resistor | 0805 | Series resistor for SD_LED header J9, adjust R-value to your type of LED and preferred brightness\nR5 | 10k Ω Resistor | 0805 | Pull-up resistor for /FLASH_OE to 3V3\nR6 | 10k Ω Resistor | 0805 | Pull-up resistor for JP2 to 3V3\nR7 | 10k Ω Resistor | 0805 | Pull-up resistor for /CFGIN to 5V\nR8 | 100k Ω Resistor | 0805 | Pull-up resistor for CRESET_N to 3V3\nRN1-RN6 | Resistor pack 10k Ω (CAY16-103J4LF) | 1206 | [CAY16-103J4LF](https://www.digikey.com/en/products/detail/bourns-inc/cay16-103j4lf/431579)\nC1 | Polarized Electrolytic Capacitor 100uF | CP_Elec_6.3x7.7 mm | [Wurth SMD WCAP-AS5H 100uF](https://www.digikey.com/en/products/detail/w%C3%BCrth-elektronik/865230245004/5727885)\nC2 | Polarized Electrolytic Capacitor 22uF | CP_Elec_5x5.8 mm | [Wurth SMD WCAP-AS5H 22uF](https://www.digikey.com/en/products/detail/w%C3%BCrth-elektronik/865230342002/5727846)\nC3-C7 | Ceramic Capacitor 10uF | 1206 |\nC8 | Ceramic Capacitor 2.2uF | 1206 |\nC9 | Ceramic Capacitor 0.47uF = 470 nF | 1206 |\nC10-C39 | Ceramic Capacitor 0.1uF = 100nF | 0805 | \nC40-C54 | Capacitor 0.01uF = 10nF | 0805 |\n\n***\n\nBOM Rev. 1B\n---------\nDesignator  | Name/Value   | Package | Notes\n-|-|-|-|\nU1 | Voltage Regulator 3.3V, \u003cbr /\u003e LM1117-3.3 or \u003cbr /\u003e AMS1117-3.3 | SOT-223 | 3.3V 1A Low Drop-Out (LDO) Voltage regulator. https://www.aliexpress.com/item/32869037691.html\nU2 | Voltage Regulator 4.3V, TPS73643DBVR or \u003cbr /\u003e ABLIC S-1200B43-M5T1U or \u003cbr /\u003e MIC5205YM5-TR ADJ (with R1,R2 and C7 populated) | SOT-23-5 | 4.3V LDO Voltage Regulator\u003cbr /\u003e* [TPS73643DBVR](https://www.mouser.com/ProductDetail/595-TPS73643DBVR) \u003cbr /\u003e* [S-1132B43-M5T1U](https://www.mouser.com/ProductDetail/628-S-1132B43-M5T1G) \u003cbr /\u003e* [MIC5205YM5-TR](https://www.mouser.com/ProductDetail/Microchip-Technology-Atmel/MIC5205YM5-TR?qs=U6T8BxXiZAUCsfGqlmZYIw%3D%3D) (Adjustable, populate R1,R2,C7)\nU3 | Inverter Schmitt Trigger 74LVC2G14GV,125 | TSOP-6/SOT457/SC-74 | * [LVC2G14GV125](https://www.mouser.com/ProductDetail/771-LVC2G14GV125)\nU4,U5,U6 | Digital Bus Switch ICs 24-Bit FET, SN74CBT16211ADGGR | TSSOP-56 | FET Level-shifter \u003cbr /\u003e * [SN74CBT16211ADGGR](https://www.mouser.com/ProductDetail/595-SNCBT16211ADGGR) \u003cbr /\u003e * [SN74CBT16811CDGG](https://www.mouser.com/ProductDetail/595-SN74CBT16811CDGG)\nU7 | XNOR gate w/ Schmitt Trigger SN74AUP1T87DCKR |TSSOP-5/SC-70-5/SOT-353-1 | Generates 7 MHz CLK from CCK XNOR CCKQ \u003cbr /\u003e * [SN74AUP1T87DCKR](https://www.mouser.com/ProductDetail/595-SN74AUP1T87DCKR)\nU8 | Gowin FPGA GW1N-UV9LQ144C6/I5 | LQFP-144 | FPGA - Field Programmable Gate Array, 8640 LE, 120 I/O \u003cbr /\u003e * [GW1N-UV9LQ144C6/I5](https://www.mouser.com/ProductDetail/192-GW1NUV9LQ144C6I5)\nU9 | Motorola CPU MC68SEC000AA20 | QFP-64 | MPU 32-bit 20MHz \u003cbr /\u003e Contact Eriond to buy a NOS CPU for a reasonable price\nU10,U11 | SRAM ISSI IS61WV20488FBLL-10TLI  | TSOP-44 | First 4 MB SRAM \u003cbr /\u003eHigh-Speed, Async, 2Mbx8, 10ns, 2.4v-3.6v, 44 Pin TSOP II, RoHS \u003cbr /\u003e * [61W20488FBLL10TI](https://eu.mouser.com/ProductDetail/870-61W20488FBLL10TI)\nU12,U13 | SRAM ISSI IS61WV20488FBLL-10TLI  | TSOP-44 | Second 4 MB (Optional) --\"-- \u003cbr /\u003e\nU14 | NOR Flash SST39LF040-55-4C-NHE-T | PLCC-32 | NOR Flash 3.0 to 3.6V (For Oktagon/Oktapus. IDE-driver) \u003cbr /\u003e * [SST39LF040554CN](https://www.mouser.com/ProductDetail/579-SST39LF040554CN) \u003cbr /\u003e (or 39LF020, 39LF010)\nU15 | SST39LF802C-55-4C-EKE | TSOP-48 | NOR Flash 3.0 to 3.6V 8Mbit Multi-Purpose Flash (for Kickstart) \u003cbr /\u003e * [S39LF802C554CEKE](https://www.mouser.com/ProductDetail/579-S39LF802C554CEKE)\nU16,U17,U18 | Bus Transceiver 74LVC245APW,118  | TSSOP-20 | * [74LVC245APW-T](https://www.mouser.com/ProductDetail/771-74LVC245APW-T)\nJ1 | Goldfingers on PCB | ENIG | Order PCB with Goldfingers, ENIG and 45 degrees chamfered edge (or chamfer the edge yourself)\nJ2 | JTAG-header | Dual row 2.54mm (2 x 5) Pin Male Header Strip | \u003ca href=\"images/SF2000_JTAG_pinout.jpg\"\u003e\u003cimg src=\"images/SF2000_JTAG_pinout.jpg\" width=\"201\" height=\"166\"\u003e\u003c/a\u003e\nJ3 | JP-header JP2,JP3,JP4 | Dual row 2.00mm (2 x 3) Pin Male Header Strip | Turbo speed selector\nJ4 | JP-header JP5 | 2.00mm (2 x 1) Pin Male Header | Generate E-CLK (if internal 68k is removed from socket)\nJ5 | IDE/ATA-header | 2.00mm 44-Pin (2x22 Pin) Straight Male Shrouded PCB Box header IDC Socket | For A2000: \u003cbr /\u003e * [Shrouded header](https://www.aliexpress.com/item/1720053014.html) \u003cbr /\u003eFor A500 internal mount a right angled female header can be used (2x25 and cut down to 2x22): \u003cbr /\u003e * [Right Angle Female Connector](https://www.aliexpress.com/item/4001286548060.html)\nJ6 | Sunrom Micro SD Card Holder | 9-pin Micro SD card slot connector | * [Sunrom Micro-SD card holder](https://www.aliexpress.com/item/32802051702.html)\nJ7 | VCC/GND Two-Pin Header 2.54mm pitch | 2.54mm pitch | VIN +5V \u003cbr /\u003e used when programming FPGA standalone (card not installed in the Amiga). Be careful with orientation, check polarity BEFORE plugging-in a phone charger or similar here.\nJ8 | JP-header JP6 | 2.00mm (2 x 1) Pin Male Header | 4/8 MB SRAM Config\nJ9,J10 | JP-header JP7,JP8 | 2.00mm (2 x 2) Pin Male Header | JP7 Autoboot IDE OFF/ON Selector, JP8 Oktagon/Oktapus. IDE-driver Selector\nJ11 | LED Two-Pin Header 2.54mm pitch | 2.54mm pitch | Driven by U3 inverter buffer when /Active on IDE is being asserted. Connect to here to drive an external HDD-LED\nJ12 | /Active signal, Single-Pin Header 2.54mm | 2.54mm pitch | /Active signal from IDE. Connect from here to a \u003cbr /\u003e * [LED-board](https://github.com/jbilander/A500_IDE_LED_board) \nJ13 | Pmod Type 2A (SPI) Female header, 12-Pin (2x6) | 2.54mm pitch | \u003ca href=\"images/SF2000_Pmod_pinout.jpg\"\u003e\u003cimg src=\"images/SF2000_Pmod_pinout.jpg\" width=\"177\" height=\"125\"\u003e\u003c/a\u003e For connecting SPI peripherals. \u003cbr /\u003e * [Right-Angled](https://www.aliexpress.com/item/1005003223096006.html) (A2000) or \u003cbr /\u003e * [Straight](https://www.aliexpress.com/item/1005003335405213.html) (A500) to not interfere with [RGBtoHDMI-adapter](https://github.com/jbilander/A500_RGBtoHDMI) inside A500\nR1 | 1.2k Ω Resistor | 0805 | Feedback resistor, Only populate if U2 is of ADJ-ustable type (e.g. MIC5205YM5-TR)\nR2 | 3k Ω Resistor | 0805 | Feedback resistor, Only populate if U2 is of ADJ-ustable type (e.g. MIC5205YM5-TR)\nR3 | 10k Ω Resistor | 0805 | Pull-up resistor for /CFGIN (5V-side)\nR4 | 10k Ω Resistor | 0805 | Pull-up resistor in RC-debounce circuit\nR5 | 10k Ω Resistor | 0805 | Series resistor in RC-debounce circuit\nR6 | ~220 Ω Resistor | 0805, 200 mW | Series resistor for IDE-LED header J11, adjust R-value to your type of LED and preferred brightness\nR7 | 1k Ω Resistor | 0805 | Pull-down resistor for IDE_IRQ\nR8 | 4.7k Ω Resistor | 0805 | Pull-up resistor for IDE_IORDY\nR9 | 10k Ω Resistor | 0805 | Pull-up resistor for JP6\nR10 | 1k Ω Resistor | 0805 | Pull-down resistor for MODE0 (Gowin FPGA boot/configure from embFlash)\nR11 | 1k Ω Resistor | 0805 | Pull-down resistor for MODE1 (Gowin FPGA boot/configure from embFlash)\nR12 | 10k Ω Resistor | 0805 | Pull-up resistor for RECONFIG_N (Gowin FPGA) and /SPI_CS (in J13 Pmod-header)\nR13 | 10k Ω Resistor | 0805 | Pull-up resistor for /ACTIVE (IDE)\nRN1-RN2,RN5 | Resistor pack 10k Ω (CAY16-103J4LF) | 1206 | * [CAY16-103J4LF](https://www.mouser.com/ProductDetail/652-CAY16-103J4LF) Pull-up resistors.\nRN3-RN4 | Resistor pack 10k Ω (CAY16-103J4LF) or 4.7k (CAY16-4701F4LF) | 1206 | * [CAY16-4701F4LF](https://www.mouser.com/ProductDetail/652-CAY16A-4701F4LF) Pull-up resistors for SD0-SD3,SD_CD,SD_CMD,JP7,JP8\nC1-C2 | Capacitor 10uF | 1206 |\nC3 | Capacitor 0.1uF = 100nF | 0805 |\nC4 | Polarized Capacitor 100uF | CP_Elec_6.3x7.7 | * [Wurth SMD WCAP-AS5H 100uF](https://www.mouser.com/ProductDetail/710-865230245004)\nC5 | Polarized Capacitor 22uF | CP_Elec_5x5.8 | * [Wurth SMD WCAP-AS5H 22uF](https://www.mouser.com/ProductDetail/710-865230342002)\nC6 | Capacitor 10uF to 0.22uF | 1206 | Check datasheet for U2 what is suitable here.\nC7 | Capacitor 0.33uF = 330nF | 1206 | (Not needed if U2 is TPS73643DBVR, check your U2-datasheet)\nC8 | Capacitor 10uF | 1206 |\nC9-C25 | Capacitor 0.1uF = 100nF | 0805 | C24 capacitor in RC-debounce circuit\nC26-C27 | Capacitor 10uF | 1206 |\nC28-C46 | Capacitor 0.01uF = 10nF | 0805 |\n\n***\n\nA SF2000 shared shopping cart with most of the stuff in the list, no 3V3-regulator though and not all birdseed (passives):\nhttps://www.mouser.com/ProjectManager/ProjectDetail.aspx?AccessID=fdb374e26b\n\n***\n\nThe FPGA used in this Accelerator board, please note it has to be the Voltage `UV` version because of 3.3V is being used for all VCC/VCCIO on the Accelerator:\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_FPGA_GW1N-UV9LQ144.png\"\u003e\n\u003cimg src=\"images/SF2000_FPGA_GW1N-UV9LQ144.png\" width=\"640\" height=\"270\"\u003e\n\u003c/a\u003e\n\n***\n\n### Ordering details (JLCPCB):\n\n\u003ca href=\"images/SF2000_JLCPCB_ordering_pic1.png\"\u003e\n\u003cimg src=\"images/SF2000_JLCPCB_ordering_pic1.png\" width=\"574\" height=\"442\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_JLCPCB_ordering_pic2.png\"\u003e\n\u003cimg src=\"images/SF2000_JLCPCB_ordering_pic2.png\" width=\"386\" height=\"220\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic5.png\"\u003e\n\u003cimg src=\"images/SF2000_pic5.png\" width=\"357\" height=\"220\"\u003e\n\u003c/a\u003e\n\n***\n### MC68SEC000 \n\nThe SF2000 is based on the MC68SEC000 CPU \u003cbr /\u003e\nhttps://www.nxp.com/docs/en/product-brief/MC68SEC000.pdf \u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic6.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic6.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\nYou can contact Eriond, https://github.com/eriond (over at A314 or Retro Tinkering or SUGA (Swedish User Group Amiga) discord) to buy a NOS MC68SEC000 at a reasonable price.\n\n***\n\n### Installing in A500 or A2000:\n\nInternal A500 installation with this adapter: \u003cbr /\u003e\nhttps://github.com/jbilander/A500_Edge_Expansion_adapter\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic7.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic7.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic8.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic8.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic9.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic9.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic10.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic10.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic11.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic11.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\nExternal A500 installation with this adapter: \u003cbr /\u003e\nhttps://github.com/jbilander/POC86\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic12.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic12.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic14.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic14.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic15.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic15.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic16.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic16.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n### A2000 Co-pro slot:\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic13.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic13.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\n***\n\n### Building\n\nFollow the dots to get the correct orientation of the chips when soldering, don't rely on the silkscreen text.\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic17.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic17.jpg\" width=\"375\" height=\"345\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\nYou can solder the 3V3 LDO and the FPGA first and then check that you can communicate via JTAG programming a simple LED-blink example or similar. +5V you can take from a USB phone-charger or similar, check polarity before you plug it in.\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic18.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic18.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\nMake sure you populate the 4V3 LDO like this if you are using `TPS73643DBVR` or `ABLIC S-1200B43-M5T1U`, populating R1,R2,C7 is only for a ADJ-regulator to achieve 4V3.\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic19.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic19.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic20.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic20.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic21.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic21.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic22.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic22.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\nFor A2000 and ribbon cable use you can solder a 44 pin IDE-header like this:\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic23.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic23.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic24.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic24.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\n### Performance\n\nSome MC68SEC000 can be overclocked to 42 MHz and running with only one wait state for the IDE/ATA interface we can reach really good performance:\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic25.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic25.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic26.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic26.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\nFlashing a ROM (in this case 3.1.4) to the FlashROM chip U15 (using LIV2's excellent sfflash-tool) and closing JP9 even better performance can be achieved:\n\u003cbr /\u003e\n\u003cbr /\u003e\nDemo video: \u003cbr /\u003e\nhttps://drive.google.com/file/d/1dCBK24LUC5VLB2dshrW_5n82D2emHB5-/view?usp=sharing\n\u003cbr /\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic27.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic27.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic28.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic28.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic29.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic29.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF2000_pic30.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic30.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003cbr /\u003e\nBut for running more stable a few wait states can be added to the IDE/ATA, \u003cbr /\u003e \nhttps://github.com/jbilander/SF2000-FW/blob/main/rtl/ata.v#L56 \u003cbr /\u003e\nresulting in a bit slower IDE:\n\u003cbr /\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_pic31.jpg\"\u003e\n\u003cimg src=\"images/SF2000_pic31.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003cbr /\u003e\nJTAG-header description:\n\u003cbr /\u003e\n\u003ca href=\"images/SF2000_JTAG_pinout_desciption.jpg\"\u003e\n\u003cimg src=\"images/SF2000_JTAG_pinout_desciption.jpg\" width=\"505\" height=\"303\"\u003e\n\u003c/a\u003e\n\n\n***\n\nHappy Hackin' \n\n***\n\n[![CC BY-SA 4.0][cc-by-sa-shield]][cc-by-sa]\n\nThis work is licensed under a\n[Creative Commons Attribution-ShareAlike 4.0 International License][cc-by-sa].\n\n[![CC BY-SA 4.0][cc-by-sa-image]][cc-by-sa]\n\n[cc-by-sa]: http://creativecommons.org/licenses/by-sa/4.0/\n[cc-by-sa-image]: https://licensebuttons.net/l/by-sa/4.0/88x31.png\n[cc-by-sa-shield]: https://img.shields.io/badge/License-CC%20BY--SA%204.0-lightgrey.svg\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Fsf2000","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjbilander%2Fsf2000","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Fsf2000/lists"}