{"id":22869043,"url":"https://github.com/jbilander/sf500","last_synced_at":"2026-01-27T21:13:38.902Z","repository":{"id":44147009,"uuid":"361744289","full_name":"jbilander/SF500","owner":"jbilander","description":"Spitfire 500, A low-end 14 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 500.","archived":false,"fork":false,"pushed_at":"2022-02-04T10:27:49.000Z","size":15555,"stargazers_count":65,"open_issues_count":9,"forks_count":6,"subscribers_count":6,"default_branch":"main","last_synced_at":"2025-03-20T23:51:20.557Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cc-by-sa-4.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jbilander.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2021-04-26T12:36:34.000Z","updated_at":"2025-01-26T18:59:37.000Z","dependencies_parsed_at":"2022-09-24T01:41:01.802Z","dependency_job_id":null,"html_url":"https://github.com/jbilander/SF500","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF500","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF500/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF500/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbilander%2FSF500/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jbilander","download_url":"https://codeload.github.com/jbilander/SF500/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246458009,"owners_count":20780678,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-13T12:45:00.834Z","updated_at":"2026-01-27T21:13:33.855Z","avatar_url":"https://github.com/jbilander.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# SF500\nSpitfire 500, A low-end 14 MHz Accelerator with IDE and 4/8 MB fast RAM for the Amiga 500.\n***\nHeavily inspired by Matthias Heinrichs' CDTV-RAM-IDE board. Many thanks to Matze for sharing his work and letting me open source this project.\n\nhttps://gitlab.com/MHeinrichs/CDTV-RAM-IDE/\n\nPlease note, if you are going to build boards and sell for profit, you will need a consent from Matthias and also from Oliver Kastl if you are going to bundle this software http://aminet.net/package/disk/misc/oktapus with the hardware (ROM-chip).\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic1.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic1.jpg\" width=\"300\" height=\"390\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic2.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic2.jpg\" width=\"300\" height=\"390\"\u003e\n\u003c/a\u003e\n\n    Board is four layers:\n    \n    signal (with 3V3-zone)\n    power plane (GND)\n    power plane (VCC)\n    signal\n\n\n***\n\nRev. 1B installed in an A500. The 7/14 MHz switch can be easily accessed if hanging out the sidecar port opening of the A500 case. This switch can also be switched while the machine is running.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic3.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic3.jpg\" width=\"308\" height=\"231\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic4.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic4.jpg\" width=\"308\" height=\"231\"\u003e\n\u003c/a\u003e\n\n***\n\nVideos: \u003cbr /\u003e\u003cbr /\u003e\nhttps://drive.google.com/file/d/1c2K9_kcEqxMMBJBd1aELfbt1fV5XXoU6/view?usp=sharing\n\nSysInfo tests running _oktagon.device_ on WB 1.3 on KS 1.3: \u003cbr /\u003e\nhttps://drive.google.com/file/d/1rewl8bivpIMPoLze_-Y7_mGYqzTiX6ET/view?usp=sharing\n\nCold boot running _oktagon.device_ and WB 1.3 on KS 1.3: \u003cbr /\u003e\nhttps://drive.google.com/file/d/1MFdxnaCo8lNMqMQ6eJMtNUMSsBB8mtb-/view?usp=sharing\n\nCold boot running _scsi.device v109.3_  (oktapussy) and ClassicWB 3.1 (with 1.3 theme) on KS 3.1: \u003cbr /\u003e\nhttps://drive.google.com/file/d/1IrmWWG6SJgc65BBj8jGnHebKbp6LAcYa/view?usp=sharing\n\n***\n\nThe CPU and the speed-select switch clears the A500 keyboard nicely when installed. Also the CF- or SD-card adapter clears the ROM-chip nicely.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic5.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic5.jpg\" width=\"308\" height=\"231\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic6.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic6.jpg\" width=\"308\" height=\"231\"\u003e\n\u003c/a\u003e\n\n***\n\n### Performance\n\n14 MHz and JP3 Open (scsi.device v109.3):\n\n\u003ca href=\"images/SF500_rev1b_pic7.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic7.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic9.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic9.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n\u003cbr /\u003e\n\u003cbr /\u003e\n\n14 MHz and JP3 Closed (oktagon.device v6.10):\n\n\u003ca href=\"images/SF500_rev1b_pic8.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic8.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic10.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic10.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nKeep in mind Kickstart 1.3 does not have FFS (Fast File System) in ROM, \nso in order to use FFS with 1.3 make a small boot-partition (e.g. ~200 MB) and format it DOS\\1, \nnot International (DOS\\3) or DirCache (DOS\\5), and not OFS (DOS\\0). For KS 3.1 I would format it FFS International (DOS\\3) or perhaps use PFS3. \u003cbr /\u003e\u003cbr /\u003e\nhttps://en.wikipedia.org/wiki/Amiga_Fast_File_System \u003cbr /\u003e\n\nAlso, do not forget to set the MaxTransfer to _0x1fe00_ and hit Enter button after typing, then save the setting. This applies to all versions except the new KS 3.2\n\n\u003ca href=\"images/SF500_rev1b_pic11.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic11.jpg\" width=\"320\" height=\"189\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic12.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic12.jpg\" width=\"264\" height=\"201\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003cbr /\u003e\nDisk's partition and filesystem information should now be stored in the RDB (Rigid Disk Block)\nfor autoboot to work under WB 1.3 with oktagon.device. \nTo install WB 1.3: Copy all content of the WB 1.3 floppy to the newly formatted Drive.\n\n\n***\n\n### How to Build:\n\nThe ROM image to burn to the AM29F040B-70JC chip can be downloaded from here: \u003cbr /\u003e\nhttps://gitlab.com/MHeinrichs/CDTV-RAM-IDE/-/blob/master/Prog/ATOKTACOMBINED.rom-512.bin\n\nThe 64 KB ROM under _Releases_ is a combined ROM I made with the instructions from the textfile [EPROM-Hack_english.txt](https://github.com/jbilander/SF500/blob/main/EPROM-Hack_english.txt) in this repo (also available in German).\nIt is 060-compatible too, not that it makes any difference for this accelerator that uses a 68000 or 68010 CPU.\n\nBurning any of the two ROM:s above will work with this Accelerator (SF500).\n\nThe last version of the Oktagon2008 from BSC is 6.12 - but still reports as 6.10. As far as I know, only the boot code has changed to be compatible with the 68060. The actual driver is still 6.10.\n\nRemember to Program the chip BEFORE you solder it down to the PCB. Do not byteswap if you are using a TL866II-Plus or similar programmer on Windows/Intel-arch, these parts are 8-bit so there is no concept of byte swapping.\n\n***\n\nSoldering: Start with all the surface mounts and then TH. I usually start with the Voltage regulator and verify the 3V3. Then the CPLD and verify JTAG-connection, doing a boundary scan with ISE-Impact. No need to solder a pin header to the JTAG connector on the PCB, just hold the connector in position and press gently. It should also be possible to use a Raspberry Pi and the program _xc3sprog_. Optionally you can put 10k or 4.7k pull-ups on R10-R12 (TMS,TDI,TCK) if you have problems connecting to the CPLD, those are 3V3 pull-ups so shouldn't damage anything using GPIO from a RPi. VCC is +5V and can be supplied through a typical usb phone-charger or similar, check polarity BEFORE you plug it in.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic13.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic13.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic14.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic14.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF500_rev1b_pic15.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic15.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic16.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic16.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nUsing some kapton tape can help to hold the chip in place while tacking it down to get everything aligned properly. For the ROM-chip I pre-tin the pads and then use hot air rework station to solder it in place.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic17.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic17.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic18.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic18.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF500_rev1b_pic19.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic19.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic20.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic20.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nWhen all the surface mount components are done it's time for the TH-pins. I use an old 68k CPU as a jig and a piece of pin strip on the other side to align the pins while soldering them in position. Press ontop the CPU somewhat at the same time when soldering for a great result.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic21.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic21.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic22.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic22.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nI used a 1.2mm thick PCB as a spacer while soldering the 44-pin IDE connector in place. This because it'll clear the Kickstart ROM chip better if the connector and hence the adapter is positioned a little higher up. The 44-pinout on the PCB is deliberately flipped/designed so that you can plug the CF or SD-adapter directly to the angled-connector the \"right\" way, no ribbon cable and no buffering is used.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic23.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic23.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic24.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic24.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF500_rev1b_pic25.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic25.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic26.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic26.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nThe final result. The mini-slide switch can optionally be soldered directly to the PCB if you prefer it that way. Only two pins are actually used, it's a normal two pin jumper with default pull-up, the third pin/hole is not connected and is only there to allow for soldering the mini-slide switch directly onto the PCB.\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic27.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic27.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\n***\n\nProgramming can now be done either this way...\n\n***\n\n\u003ca href=\"images/SF500_rev1b_pic28.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic28.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic29.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic29.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF500_rev1b_pic30.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic30.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_rev1b_pic31.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_pic31.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\n...or like in picture below...it requires the Amiga PSU to be turned ON to provide +5V to the Accelerator, do not connect any external +5V here:\n\n***\n\n\u003ca href=\"images/SF500_rev1a_pic4.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1a_pic4.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nJumpers:\n\n    /CFGIN = This jumper is to activate autoconfig (active low with 1k pull-down resistor R3). No jumper here means no RAM nor IDE will be autoconfigured. \n    SW1 = CPU speed toggle between 7 or 14 MHz, default 10k pull-up means 14 MHz\n    JP2 = Selects between 4 or 8 MB fast ram autoconfig, 8 MB requires U7,U8 populated too.\n    JP3 = Selects between IDE driver oktagon.device or scsi.device_v109.3 (oktapussy)\n    JP4 = Selects between Autoboot or Not, jumper Closed means autoconfigure will not load the ROM-vector (the JP3-selected driver).\n\n***\n\nSynthesis Summary:\n\n\u003ca href=\"images/SF500_rev1b_synthesis_summary.jpg\"\u003e\n\u003cimg src=\"images/SF500_rev1b_synthesis_summary.jpg\" width=\"512\" height=\"384\"\u003e\n\u003c/a\u003e\n\nZipped JED-file (_main_top.jed_) available under _Releases_\n\nNew firmware released 2021-12-22 that supports DMA from A590, available under _Releases_\n\n***\n\n### SF500 and A590\nWith the updated firmware it's now possible to use an A590 (on the A500 expansion edge) togheter with a SF500.\n\u003cbr /\u003e\nYou will need to solder/connect a jumper-wire from the CFGOUT-goldfinger-pad and run it to the CFGIN-pin on the SF500. This will asure that there will be no conflict during AutoConfig cycles. They will be daisy-chained meaning the A590 configures first and the SF500 is second in line.\n\n\u003ca href=\"images/SF500_and_A590_pic1.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic1.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic2.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic2.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nHaving the A590 jumper set to enable onboard memory (2MB in picures below) is not optimal in this case since that memory will automatically be used first by the system. You will have to set the jumper (JP2) to _ON_ (4MB) on the SF500 in this scenario but as you can see only 0.84 mips here:\n\n\u003ca href=\"images/SF500_and_A590_pic3.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic3.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic4.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic4.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic5.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic5.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nIn this case it's much better to set the A590 jumper to _Amnesia_ and hence \"only\" use the 4MB or 8MB from the SF500. Don't worry the A590 can then DMA (Direct Memory Access) into that memory:\n\n***\n\n\u003ca href=\"images/SF500_and_A590_pic6.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic6.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic7.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic7.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nWith the SF500 set to _Amnesia_ we get the full performance at 14 MHz and we can use the Hard Drive in the A590 either to boot from or just as a second harddrive for storage or backup (this depends on boot prio setting). Both the Oktagon.device and the Oktapussy scsi.device can co-exist with the A590 driver. As you can see the oktapussy driver takes the name _2nd_ scsi device here:\n\n***\n\n\u003ca href=\"images/SF500_and_A590_pic8.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic8.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic9.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic9.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003cbr /\u003e\n\u003ca href=\"images/SF500_and_A590_pic10.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic10.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic11.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic11.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n\n***\n\nChanging boot priority in HDToolBox let us select which drive to boot from. Please note, I used prio 10 here but if you still want the DF0 floppy drive as the first device (you probably will) then you can't put in a number above 5. Keep it below 5 since DF0 has boot priority 5 by default, this was just for testing, remember to press Enter after entering the new value in the box and then hit the _Save Changes to Drive_ button before you do a reboot.\n\n\u003ca href=\"images/SF500_and_A590_pic12.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic12.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\u003ca href=\"images/SF500_and_A590_pic13.jpg\"\u003e\n\u003cimg src=\"images/SF500_and_A590_pic13.jpg\" width=\"256\" height=\"192\"\u003e\n\u003c/a\u003e\n\n***\n\nA short video showing boot from A590 in _Amnesia_ mode and copying a 2.2 MB file from the SF500 IDE drive to the A590 XT drive. \u003cbr /\u003e\u003cbr /\u003e\nhttps://drive.google.com/file/d/1oLW0H9GmMaRv7rbYKLQVwRg4RvrDyU3E/view?usp=sharing\n\u003cbr /\u003e\u003cbr /\u003e\nHere a short video booting from the SF500 IDE drive (with higher boot prio set) than the A590 (still in _Amnesia_ mode). The A590 harddrive is automatically mounted and available to the system after startup:\u003cbr /\u003e\u003cbr /\u003e\nhttps://drive.google.com/file/d/13qs9DawRrVdHNif9vCZlh3xlq8YgDj_f/view?usp=sharing\n\n***\n\nBOM Rev. 1B\n---------\nPosition  | Name/Value   | Package | Notes\n-|-|-|-|\nU1 | 64Pcs socket pins for Round Plug 0.5mm Diameter | 100Pcs | IC Leads Receptacle, gold or nickel plated, used as TH Pin Header. https://www.aliexpress.com/item/1005002830101899.html\nU2 | CPU Socket, 2 x 32 Female Pin Header 2.54mm pitch | 2 x Single Row 40Pin | Round Female Pin Header gold or nickel plated machined pins.\nU3 | Voltage Regulator 3.3V, LM1117-3.3 or AMS1117-3.3 | SOT-223 | 3.3V 1A Low Drop-Out (LDO) Voltage regulator.\nU4 | NB3N502 - 14 MHz to 190 MHz PLL Clock Multiplier | SOIC-8 | PLL with CLKOUT and at the same time output the input aligned reference clock signal (REF).\nU5-U6 | 2 x CY62167G-45ZXI or 2 x CY62167ELL-45ZXI | 48-pin TSOP-I configurable as 1M × 16 or 2M × 8 SRAM |  First 4 MB. Cost $3 / Pcs from here https://www.aliexpress.com/item/1005003256658439.html (verified ok)\nU7-U8 | 2 x CY62167G-45ZXI or 2 x CY62167ELL-45ZXI | | (Optional) Second 4 MB.\nU9 | XC95144XL-TQ100 | TQFP-100_14x14mm_P0.5mm | IC Xilinx CPLD 144MC 10NS 100TQFP, XC95144XL-10TQG100C\nU10 | 29F040 or 29F010 | PLCC-32_11.4x14.0mm_P1.27mm | e.g. AM29F040B-70JC or AS29CF010-55CCIN\nU11 | 74HCT2G14 | TSOP-6 | Dual inverting Schmitt trigger\nR1 | 10k | 1206 | /VPA Pull-up resistor\nR2 | 10k | 1206 | JP2 Pull-up resistor (P74)\nR3 | 1k | 1206 | /CFGIN Pull-down resistor (P70)\nR4 | 33 Ohm or 0 Ohm | 1206 | (Optional) /CFGOUT series resistor (P68)\nR5 | 10k | 1206 | JP3 Pull-up resistor (Line A15 ROM)\nR6 | 4.7k | 1206 | IDE_IORDY Pull-up resistor (P12)\nR7 | 1k | 1206 | IDE_IRQ Pull-down resistor (P27)\nR8 | 4.7k | 1206 | /AS_CPU Pull-up resistor (P79)\nR9 | 1k | 1206 | /DTACK_CPU Pull-up resistor (P13)\nR10 | 4.7k or 10k | 0805 | (Optional) TMS 3.3V Pull-up resistor (P47)\nR11 | 4.7k or 10k | 0805 | (Optional) TDI 3.3V Pull-up resistor (P45)\nR12 | 4.7k or 10k | 0805 | (Optional) TCK 3.3V Pull-up resistor (P48)\nR13 | 10k | 0805 | SW1 Pull-up resistor debounce circuit (P76)\nR14 | 10k | 0805 | resistor in (RC) debounce circuit\nR15 | 10k | 1206 | JP4 Pull-up (P67)\nR16 | 4.7k or 10k | 0805 | (Optional) CFGIN Pull-up (P70)\nC1 | 10uF | 1206 | capacitor for Voltage regulator\nC2 | 10uF | 1206 | capacitor for Voltage regulator\nC3 | 0.1uF = 100nF | 0805 | capacitor for Voltage regulator\nC4 | 0.1uF = 100nF | 0805 | decoupling capacitor for U4 (PLL)\nC5-C6 | 0.1uF = 100nF | 0805 | decoupling capacitors for U5-U6 (first 2 x SRAM)\nC7-C8 | 0.1uF = 100nF | 0805 | decoupling capacitors for U7-U8 (if populated, second 2 x SRAM)\nC9-C12 | 0.1uF = 100nF | 0805 | decoupling capacitors for U9 (CPLD)\nC13 | 10uF | 1206 | capacitor for VCC-pin\nC14 | 10uF | 1206 | capacitor for IDE VCC-pin\nC15 | 0.1uF = 100nF | 0805 | decoupling capacitor for U10 (ROM)\nC16 | 0.1uF = 100nF | 0805 | capacitor in (RC) debounce circuit (SW1)\nC17 | 0.1uF = 100nF | 0805 | decoupling capacitor for U11 (Schmitt trigger inverter)\nJ1 | JTAG Pin Header 2.54mm pitch | Single row 6pin | (Optional) Pressing JTAG-header pins against holes while programming is enough.\nJ2 | External Pin Header 2.54mm pitch | Single row 5pin angled or straight | 2.54mm Jumper on CFGIN-pin needed for enable Autoconfig unless daisy chained.\nSW1 (J3) | 3Pin Header 2.54mm pitch | Single row 3pin | Pin header with jumper select 7/14MHz or On-Off mini slide switch SS12D00 3pin 1P2T 2 Position toggle switch. Handle length: 3mm-6mm\nJ4 | 2.0mm Pitch Right Angle IDE-socket | Double Row (2 x 22) Female 44pin header socket | 2 x 25 or 2 x 40, pull pin 45, 46 using a plier and cut with a hacksaw = Pin header 2 x 22. https://www.aliexpress.com/item/4001286548060.html\n\n***\n\nHappy Hackin' \n\n***\n\n[![CC BY-SA 4.0][cc-by-sa-shield]][cc-by-sa]\n\nThis work is licensed under a\n[Creative Commons Attribution-ShareAlike 4.0 International License][cc-by-sa].\n\n[![CC BY-SA 4.0][cc-by-sa-image]][cc-by-sa]\n\n[cc-by-sa]: http://creativecommons.org/licenses/by-sa/4.0/\n[cc-by-sa-image]: https://licensebuttons.net/l/by-sa/4.0/88x31.png\n[cc-by-sa-shield]: https://img.shields.io/badge/License-CC%20BY--SA%204.0-lightgrey.svg\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Fsf500","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjbilander%2Fsf500","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbilander%2Fsf500/lists"}