{"id":13682490,"url":"https://github.com/jbush001/LispMicrocontroller","last_synced_at":"2025-04-30T09:32:50.495Z","repository":{"id":2122042,"uuid":"3064649","full_name":"jbush001/LispMicrocontroller","owner":"jbush001","description":"A microcontroller that natively executes a simple LISP dialect","archived":false,"fork":false,"pushed_at":"2024-01-22T01:50:41.000Z","size":375,"stargazers_count":89,"open_issues_count":7,"forks_count":12,"subscribers_count":9,"default_branch":"master","last_synced_at":"2024-11-07T22:02:29.957Z","etag":null,"topics":["cpu","fpga","hardware","lisp","microcontroller","verilog"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jbush001.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2011-12-28T19:39:57.000Z","updated_at":"2024-09-24T14:38:47.000Z","dependencies_parsed_at":"2024-08-02T13:22:16.282Z","dependency_job_id":"6be7047c-be61-418c-b737-91a2119c8bcd","html_url":"https://github.com/jbush001/LispMicrocontroller","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbush001%2FLispMicrocontroller","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbush001%2FLispMicrocontroller/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbush001%2FLispMicrocontroller/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jbush001%2FLispMicrocontroller/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jbush001","download_url":"https://codeload.github.com/jbush001/LispMicrocontroller/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":224206087,"owners_count":17273387,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["cpu","fpga","hardware","lisp","microcontroller","verilog"],"created_at":"2024-08-02T13:01:46.951Z","updated_at":"2024-11-12T02:30:51.368Z","avatar_url":"https://github.com/jbush001.png","language":"Python","readme":"[![CI](https://github.com/jbush001/LispMicrocontroller/workflows/CI/badge.svg)](https://github.com/jbush001/LispMicrocontroller/actions?query=workflow%3ACI)\n[![Codacy Badge](https://api.codacy.com/project/badge/Grade/8f4aff19a2d242f892acc10b98950f46)](https://www.codacy.com/app/jbush001/LispMicrocontroller?utm_source=github.com\u0026amp;utm_medium=referral\u0026amp;utm_content=jbush001/LispMicrocontroller\u0026amp;utm_campaign=Badge_Grade)\n\nThis is a simple microcontroller that runs a compiled LISP dialect.  Details of operation are in the [wiki](https://github.com/jbush001/LispMicrocontroller/wiki).\n\n## Running in simulation\n\nThis uses Icarus Verilog for simulation (http://iverilog.icarus.com/). Tests are located in the tests/ directory. Run them as follows:\n\n    make test\n\nThe test runner searches files for patterns that begin with 'CHECK:'. The output of the program will be compared to whatever comes after this declaration. If they do not match, an error will be flagged.\n\n### Manually running a program\n\n* Compile the LISP sources.\nThis produces two files: program.hex, which has the raw program machine code and is loaded by the simulator, and program.lst, which is informational and shows details of the generated code.  For example:\n\n        ./compile.py tests/test1.lisp\n\nNote that any writes to register index 0 will be printed to standard out by the simulation test harness, which is how most simulation tests work.\n\n* Run simulation.\nThe simulator will read rom.hex each time it starts.\n\n        vvp sim.vvp\n\n## Running in hardware\n\nThis has only been tested under Quartus/Altera with the Cyclone II starter kit.  There are a couple of projects located\nunder the fpga/ directory:\n  - 7seg: simple program that displays numbers on the 4-digit, 7 segment display\n  - game: a little arcade-style demo with animated sprites\n\n### To build:\n\n* Compile the LISP sources.\nThese are located in the project directory, but must be compiled from the top directory.\nFor example, from LispMicrocontroller/\n\n        ./compile.py fpga/game/game.lisp\n\n    rom.hex will be created in the top level LispMicrocontroller/ directory.\n\n* Synthesize the design\nOpen the program file (for example, fpga/game/game.qpf).  Note that the synthesis tools will\nread rom.hex to create the values for program ROM.  If you recompile the LISP sources (thereby changing rom.hex), the design must be re-synthesized.\n\n* Run using the programmer included with Quartus.\n","funding_links":[],"categories":["Python"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbush001%2FLispMicrocontroller","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjbush001%2FLispMicrocontroller","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjbush001%2FLispMicrocontroller/lists"}