{"id":22975854,"url":"https://github.com/jc-ll/reggae_v2","last_synced_at":"2025-06-17T15:44:12.022Z","repository":{"id":146879962,"uuid":"452724355","full_name":"JC-LL/reggae_v2","owner":"JC-LL","description":null,"archived":false,"fork":false,"pushed_at":"2022-02-01T11:07:59.000Z","size":11877,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-07T22:49:56.313Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Ruby","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/JC-LL.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-01-27T14:54:25.000Z","updated_at":"2022-01-27T23:01:43.000Z","dependencies_parsed_at":null,"dependency_job_id":"61780b02-b95d-4fa8-a507-93c02fc23d76","html_url":"https://github.com/JC-LL/reggae_v2","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JC-LL%2Freggae_v2","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JC-LL%2Freggae_v2/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JC-LL%2Freggae_v2/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JC-LL%2Freggae_v2/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/JC-LL","download_url":"https://codeload.github.com/JC-LL/reggae_v2/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246777833,"owners_count":20832032,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-12-15T00:39:54.025Z","updated_at":"2025-04-02T08:14:18.629Z","avatar_url":"https://github.com/JC-LL.png","language":"Ruby","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Reggae : FPGA register map VHDL generation\n\n## What is it ?\nReggae is a simple tool that generates a System-on-Chip architecture from a a description of its memory map.\n\nThe tool is especially targeted to quick prototyping of early demonstrators on FPGA.\n\n## Memory map specification : s-expression based\nThe memory map, specified by the user, is described in a s-expression based file.\n\nA full example is provided in tests directory. A simple IP interface can be as simple as :\n\n```\n  (ip \"switches\"\n    (range 0x1 0x1)\n    (reg \"switches\"\n      (address 0x1)\n      (sampling \"sig_switches\")\n      (init 0xcafebabe)\n    )\n  )\n```\nHere we have simply asked Reggae to generate an IP named \"switches\", with a single register, also named \"switches\", that reset to default value 0xcafebabe. This register samples a signal named \"sig_switches\", that will be user-defined, probably connected to actual switches !\n\nMore detailed low-level specification can be used : bits and bitfields, toggling etc\n\n```\n(ip \"robot\"\n  (range 0x202 0x203)\n  (reg \"control\"\n    (address 0x202)\n    (size 5)\n    (init 0xdeadbeef)\n    (bit 0\n      (name \"go\")\n      (toggling true)\n    )\n    (bit 1\n      (name \"stop\")\n    )\n    (bit 2\n      (name \"light_on\")\n    )\n    (bit 3\n      (name \"turn_right\")\n    )\n    (bit 4\n      (name \"turn_left\")\n    )\n  )\n  (reg \"status\"\n    (address 0x203)\n    (init 0x0)\n    (bit 0\n      (name \"stopped\")\n      (sampling \"robot_stopped\")\n    )\n    (bit 1\n      (name \"failure\")\n      (sampling \"robot_failure\")\n    )\n    (bitfield 2..31\n      (name \"loch\")\n      (sampling \"robot_loch\")\n    )\n  )\n\n)\n```\n\nReggae will then create the following architecture, as well as testbench and synthesis files (for Vivado, today for Nexysa7).\n\n## SoC architecture\n\nThe SoC template is given as example below.\n\n\u003cp align=\"center\"\u003e\n  \u003cimg src=\"./doc/schematic.png\" /\u003e\n\u003c/p\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjc-ll%2Freggae_v2","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjc-ll%2Freggae_v2","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjc-ll%2Freggae_v2/lists"}