{"id":15654018,"url":"https://github.com/jeffdecola/my-verilog-examples","last_synced_at":"2026-02-17T21:33:46.568Z","repository":{"id":54658538,"uuid":"174155074","full_name":"JeffDeCola/my-verilog-examples","owner":"JeffDeCola","description":"A place to keep my synthesizable verilog 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Latest](https://img.shields.io/github/v/tag/jeffdecola/my-verilog-examples)](https://github.com/JeffDeCola/my-verilog-examples/tags)\n[![jeffdecola.com](https://img.shields.io/badge/website-jeffdecola.com-blue)](https://jeffdecola.com)\n[![MIT License](https://img.shields.io/:license-mit-blue.svg)](https://jeffdecola.mit-license.org)\n\n_A place to keep my synthesizable verilog examples._\n\nTable of Contents\n\n* [OVERVIEW](https://github.com/JeffDeCola/my-verilog-examples#overview)\n* [BASIC CODE](https://github.com/JeffDeCola/my-verilog-examples#basic-code)\n  * COMBINATIONAL LOGIC\n  * SEQUENTIAL LOGIC\n* [COMBINATIONAL LOGIC](https://github.com/JeffDeCola/my-verilog-examples#combinational-logic)\n  * ALUs\n  * DATA OPERATORS\n  * DECODERS \u0026 ENCODERS\n  * MULTIPLEXERS \u0026 DEMULTIPLEXERS\n* [FPGA DEVELOPMENT BOARDS](https://github.com/JeffDeCola/my-verilog-examples#fpga-development-boards)\n  * BUTTONS\n* [SEQUENTIAL LOGIC](https://github.com/JeffDeCola/my-verilog-examples#sequential-logic)\n  * ARBITERS\n  * COUNTERS\n  * FINITE SATE MACHINES\n  * MEMORY\n  * REGISTERS\n  * SHIFTERS\n* [SYSTEMS](https://github.com/JeffDeCola/my-verilog-examples#systems)\n  * MICROPROCESSORS\n  * PIPELINES\n\nDocumentation and Reference\n\n* [verilog](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/development/languages/verilog-cheat-sheet)\n* [iverilog](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/iverilog-cheat-sheet)\n  is a free tool for simulation and synthesis\n* [GTKWave](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/gtkwave-cheat-sheet)\n  is a free HDL waveform viewer\n* [xilinx vivado](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/synthesis/xilinx-vivado-cheat-sheet)\n  is a complete IDE for synthesis and analysis of HDL designs\n* [digilent ARTY-S7](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/development/fpga-development-boards/digilent-arty-s7-cheat-sheet)\n  is a FPGA development board\n* My\n  [Master's Thesis](https://github.com/JeffDeCola/my-masters-thesis)\n  has an explanation of HDLs and how they fit into frameworks\n* My\n  [Master's Thesis](https://github.com/JeffDeCola/my-masters-thesis)\n  also has my design of a\n  [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)\n* This repos\n  [github webpage](https://jeffdecola.github.io/my-verilog-examples/)\n  _built with\n  [concourse](https://github.com/JeffDeCola/my-verilog-examples/blob/master/ci-README.md)_\n\n## OVERVIEW\n\n_Each example uses\n[iverilog](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/iverilog-cheat-sheet)\nto simulate and\n[GTKWave](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/simulation/gtkwave-cheat-sheet)\nto view the waveform. I also used\n[Xilinx Vivado](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/tools/synthesis/xilinx-vivado-cheat-sheet)\nto synthesize and program these verilog examples on a\n[Digilent ARTY-S7](https://github.com/JeffDeCola/my-cheat-sheets/tree/master/hardware/development/fpga-development-boards/digilent-arty-s7-cheat-sheet)\nFPGA development board._\n\nI declare my ports as follows because that's what the synthesis tools want.\nWho am I to argue.\n\n```verilog\n    module NAME (\n        input             a,     // Input A\n        input       [7:0] b,     // Input B\n        output reg  [3:0] y);    // Output Y\n```\n\nAlso, I would stay away from asynchronous design.  It can have problems\nwhen you synthesize to an FPGA.\n\n```verilog\n\n    // DO THIS\n    always @(posedge clk) begin\n        if (~reset) begin\n            ...\n\n    // NOT THIS\n    always @(posedge clk or negedge reset) begin\n\n```\n\nEach example has the following 4 files,\n\n* `*.v` - The verilog code files(s)\n* `*.vh` - A header file listing the included verilog files\n* `*_tb.v` - The verilog testbench code\n* `*_tb.tv` - Test vectors used with the testbench\n\nThe artifacts created are,\n\n* `*_tb.vvp` - The verilog compiled code to be used by the simulator\n* `*_tb.vcd` - The dump of the waveform data\n* `*_tb.gtkw` - The GTKWave saved waveform\n\nWhere the testbench structure is,\n\n![testbench-structure.svg](docs/pics/testbench-structure.svg)\n\n## BASIC CODE\n\n* COMBINATIONAL LOGIC\n\n  * [and2](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/combinational-logic/and2)\n\n    _2-input AND gate used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [nand4](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/combinational-logic/nand4)\n\n    _4-input NAND gate used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [nor2](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/combinational-logic/nor2)\n\n    _2-input NOR gate used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [not1](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/combinational-logic/not1)\n\n    _NOT gate used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [or2](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/combinational-logic/or2)\n\n    _2-input OR gate used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [xor2](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/combinational-logic/xor2)\n\n    _2-input XOR gate used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n* SEQUENTIAL LOGIC\n\n  * [sr_latch](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/sr_latch)\n\n    _A sr (set ready) latch which is **level-triggered**\n    that can be set and reset.\n    The latch forms the basic building block\n    of other types of latches and flip-flops._\n\n  * [sr_flip_flop](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/sr_flip_flop)\n\n    _A sr (set ready) flip-flop which is **pulse-triggered**\n    can be set and reset._\n\n  * [jk_flip_flop](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/jk_flip_flop)\n\n    _A jk flip-flop which is **pulse-triggered**\n    can be set, reset and toggled.\n    This has a race condition when clock is high._\n\n  * [jk_flip_flop_pulse_triggered](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/jk_flip_flop_pulse_triggered)\n\n    _A pulse-triggered jk flip-flop (cascading)\n    can be set, reset and toggled._\n\n  * [jk_flip_flop_pos_edge_sync_clear](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/jk_flip_flop_pos_edge_sync_clear)\n\n    _A **posedge-triggered** jk flip-flop\n    with synchronous clear\n    used in my\n    [jeff_74x161](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/counters/jeff_74x161)._\n\n  * [t_flip_flop](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/t_flip_flop)\n\n    _A t flip-flop which is **pulse-triggered**\n    can be toggled.\n    This has a race condition when clock is high._\n\n  * [d_flip_flop](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/d_flip_flop)\n\n    _A d flip-flop which is **pulse-triggered**\n    can save input data on output._\n\n  * [d_flip_flop_pulse_triggered](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/d_flip_flop_pulse_triggered)\n\n    _A **pulse-triggered** d flip-flop (cascading)\n    can save input data on output._\n\n  * [d_flip_flop_pos_edge_sync_en](https://github.com/JeffDeCola/my-verilog-examples/tree/master/basic-code/sequential-logic/d_flip_flop_pos_edge_sync_en)\n\n    _A **posedge-triggered** d flip-flop\n    with synchronous enable\n    used in my\n    [jeff_74x377](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/registers/jeff_74x377)._\n\n## COMBINATIONAL LOGIC\n\n* ALUs\n\n  * [jeff_74x181](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/alus/jeff_74x181)\n\n    _4-bit alu (arithmetic logic unit) and function generator.\n    Provides 16 binary logic operations and 16 arithmetic operations\n    on two 4-bit words.\n    Based on the 7400-series integrated circuits used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n* DATA OPERATORS\n\n  * [full_adder](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/data-operators/full_adder)\n\n    _A 2-bit full-adder._\n\n  * [half_adder](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/data-operators/half_adder)\n\n    _A 2-bit half-adder._\n\n* DECODERS \u0026 ENCODERS\n\n  * [encoder_8_3](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/decoders-and-encoders/encoder_8_3)\n\n    _Encoder - Eights inputs (1 hot) encodes to output._\n\n  * [decoder_3_8](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/decoders-and-encoders/decoder_3_8)\n\n    _Decoder - Three inputs decodes to 1 of 8 outputs (hot)._\n\n  * [encoder_to_decoder](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/decoders-and-encoders/encoder_to_decoder)\n\n    _Combining the\n    [encoder_8_3](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/decoders-and-encoders/encoder_8_3)\n    to the\n    [decoder_3_8](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/decoders-and-encoders/decoder_3_8)\n    to prove the input will equal\n    the output._\n\n* MULTIPLEXERS \u0026 DEMULTIPLEXERS\n\n  * [demux_1x4](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/demux_1x4)\n\n    _Demultiplexer - One input, four outputs._\n\n  * [jeff_74x151](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/jeff_74x151)\n\n    _8-line to 1-line data selector/multiplexer.\n    Based on the 7400-series integrated circuits used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [jeff_74x157](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/jeff_74x157)\n\n    _Quad 2-line to 1-line data selector/multiplexer, non-inverting outputs.\n    Based on the 7400-series integrated circuits used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my_verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [mux_4x1](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/mux_4x1)\n\n    _Multiplexer - Four inputs, one output._\n\n  * [mux_to_demux](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/mux_to_demux)\n\n    _Combining the\n    [mux_4x1](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/mux_4x1)\n    to the\n    [demux_1x4](https://github.com/JeffDeCola/my-verilog-examples/tree/master/combinational-logic/multiplexers-and-demultiplexers/demux_1x4)\n    to prove the input will equal\n    the output (for the selected output)._\n\n## FPGA DEVELOPMENT BOARDS\n\n* BUTTONS\n\n  * [buttons](https://github.com/JeffDeCola/my-verilog-examples/tree/master/fpga-development-boards/buttons/buttons)\n\n    _A few different ways to use buttons on a FPGA development board._\n\n## SEQUENTIAL LOGIC\n\n* ARBITERS\n\n  * [priority_arbiter](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/arbiters/priority_arbiter)\n\n    _A three level priority arbiter with asynchronous reset._\n\n* COUNTERS\n\n  * [jeff_74x161](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/counters/jeff_74x161)\n\n    _Synchronous presettable 4-bit binary counter, asynchronous clear.\n    Based on the 7400-series integrated circuits used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n* FINITE STATE MACHINES\n\n  * [mealy_state_machine](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/finite-state-machines/mealy_state_machine)\n\n    _Recognize the pattern 00110 in a serial stream.\n    Output depends on current state and current inputs._\n\n  * [moore_state_machine](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/finite-state-machines/moore_state_machine)\n\n    _Recognize the pattern 00110 in a serial stream.\n    Output depends on current state only._\n\n* MEMORY\n\n  * [single_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/single_port_ram_synchronous)\n\n    _Single-port synchronous RAM._\n\n  * [dual_port_ram_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_synchronous)\n\n    _Dual-port synchronous RAM._\n\n  * [dual_port_ram_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/dual_port_ram_asynchronous)\n\n    _Dual-port asynchronous RAM using two different clocks._\n\n  * [fifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_synchronous)\n\n    _A synchronous fifo using dual-port synchronous RAM._\n\n  * [fifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/fifo_asynchronous)\n\n    _An asynchronous fifo using dual-port asynchronous RAM._\n\n  * [lifo_synchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_synchronous)\n\n    _A synchronous lifo using dual-port synchronous RAM._\n\n* REGISTERS\n\n  * [jeff_74x377](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/registers/jeff_74x377)\n\n    _8-bit register, clock enable.\n    Based on the 7400-series integrated circuits used in my\n    [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)._\n\n  * [simple_8_bit_register](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/registers/simple_8_bit_register)\n\n    _A simple 8-bit register with synchronous load and clear._\n\n* SHIFTERS\n\n  * [left_shift_register](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/shifters/left_shift_register)\n\n    _A 4-bit left shift register._\n\n## SYSTEMS\n\n* MICROPROCESSORS\n\n  * [programable_8_bit_microprocessor](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/microprocessors/programable_8_bit_microprocessor)\n\n    _A programable 8-bit microprocessor. Originally designed in VHDL for part of\n    [my master's thesis](https://github.com/JeffDeCola/my-masters-thesis)._\n\n* PIPELINES\n\n  * [simple_pipeline](https://github.com/JeffDeCola/my-verilog-examples/tree/master/systems/pipelines/simple_pipeline)\n\n    _A simple pipeline._\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjeffdecola%2Fmy-verilog-examples","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjeffdecola%2Fmy-verilog-examples","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjeffdecola%2Fmy-verilog-examples/lists"}