{"id":13537136,"url":"https://github.com/jhshi/openofdm","last_synced_at":"2026-01-16T12:16:32.101Z","repository":{"id":25833410,"uuid":"89514111","full_name":"jhshi/openofdm","owner":"jhshi","description":"Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.","archived":false,"fork":false,"pushed_at":"2023-01-29T05:08:45.000Z","size":28052,"stargazers_count":406,"open_issues_count":15,"forks_count":198,"subscribers_count":23,"default_branch":"master","last_synced_at":"2025-04-02T04:34:41.209Z","etag":null,"topics":["802-11","ofdm","verilog"],"latest_commit_sha":null,"homepage":"http://openofdm.rtfd.io","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jhshi.png","metadata":{"files":{"readme":"Readme.rst","changelog":null,"contributing":null,"funding":null,"license":"LICENSE.txt","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2017-04-26T18:32:11.000Z","updated_at":"2025-03-27T07:01:32.000Z","dependencies_parsed_at":"2023-02-15T21:00:28.693Z","dependency_job_id":null,"html_url":"https://github.com/jhshi/openofdm","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/jhshi/openofdm","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jhshi%2Fopenofdm","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jhshi%2Fopenofdm/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jhshi%2Fopenofdm/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jhshi%2Fopenofdm/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jhshi","download_url":"https://codeload.github.com/jhshi/openofdm/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jhshi%2Fopenofdm/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":28478536,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-01-16T11:59:17.896Z","status":"ssl_error","status_checked_at":"2026-01-16T11:55:55.838Z","response_time":107,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["802-11","ofdm","verilog"],"created_at":"2024-08-01T09:00:55.499Z","updated_at":"2026-01-16T12:16:32.085Z","avatar_url":"https://github.com/jhshi.png","language":"Verilog","funding_links":[],"categories":["Accelerators","Verilog"],"sub_categories":[],"readme":"OpenOFDM\n========\n\nThis project contains a Verilog implementation of 802.11 OFDM PHY decoder.\nFeatures are:\n\n - Fully synthesizable (tested on Ettus Research USRP N210 platform)\n - Full support for legacy 802.11a/g\n - Support 802.11n for MCS 0 - 7 @ 20 MHz bandwidth\n - Cross validation with included Python decoder \n - Modular design for easy modification and extension\n\nSee full documentation at http://openofdm.readthedocs.io.\n\nEnvironment Setup\n-----------------\n\nThis project has the following dependencies:\n\n - `Icarus Verilog \u003chttp://iverilog.icarus.com/\u003e`_: for compiling Verilog files and simulation.\n - `GtkWave \u003chttp://iverilog.icarus.com/\u003e`_: for wave form visualization.\n\n\nInput and Output\n----------------\n\nIn a nutshell, the top level ``dot11`` Verilog module takes 32-bit I/Q samples\n(16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling\nrate is 20 MSPS and the clock rate is 100 MHz. This means this module expects\none pair of I/Q sample every 5 clock ticks.\n\n\nLicense\n-------\n\n`Apache License 2.0 \u003chttps://www.apache.org/licenses/LICENSE-2.0\u003e`_\n\nFAQs\n----\n\n**Q: Is there any need to change host driver UHD to incorporate new changes in\nFPGA?**\n\nA: No. In fact OpenOFDM relies on the current UHD-USRP communication mechanism.\nHowever, since the logic of the FPGA is changed in OpenOFDM, its behavior is\nalso different. For instance, utilities such as ``rx_samples_to_file`` do not\nwork as expected since the FPGA in OpenOFDM does not dumping RF signals back to\nhost.\n\n**Q: Any example code to communicate with OFDM core in FPGA from host?**\n\nA: OpenOFDM FPGA module is configurable via USRP user setting registers\n(``set_user_reg`` function). The\nregister address definition is in `common_params.v\n\u003chttps://github.com/jhshi/openofdm/blob/master/verilog/common_params.v\u003e`_. The\nwhole OpenOFM FPGA module takes 32 bit I/Q samples and outputs decoded bytes. It\nis supposed to be placed in the receive chain of the USRP (e.g.,\n``custom_dsp_rx.v``.\n\n\n**Q: Is there any change in ZPU firmware?**\n\nA: No.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjhshi%2Fopenofdm","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjhshi%2Fopenofdm","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjhshi%2Fopenofdm/lists"}