{"id":17774659,"url":"https://github.com/jiegec/loongarch-csr","last_synced_at":"2025-04-01T15:33:43.183Z","repository":{"id":211682957,"uuid":"729728518","full_name":"jiegec/loongarch-csr","owner":"jiegec","description":"LoongArch CSR 和 IOCSR 整理","archived":false,"fork":false,"pushed_at":"2024-01-06T14:44:38.000Z","size":12,"stargazers_count":6,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-07T09:45:45.694Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jiegec.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-12-10T06:44:44.000Z","updated_at":"2024-10-22T14:34:39.000Z","dependencies_parsed_at":"2024-01-06T15:40:32.080Z","dependency_job_id":null,"html_url":"https://github.com/jiegec/loongarch-csr","commit_stats":null,"previous_names":["jiegec/loongarch-csr"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Floongarch-csr","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Floongarch-csr/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Floongarch-csr/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Floongarch-csr/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jiegec","download_url":"https://codeload.github.com/jiegec/loongarch-csr/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246662820,"owners_count":20813790,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-26T21:51:52.925Z","updated_at":"2025-04-01T15:33:43.162Z","avatar_url":"https://github.com/jiegec.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# LoongArch CSR 和 IOCSR 整理\n\n## CSR\n\n### GTLBC (0x15, Guest TLB Control)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.7-rc1)\n\n字段：\n\n1. GMTLBSZ: [5:0]: Guest MTLB Size. We currently don't know its exact encoding.\n2. USETGID(renamed from USERID): [12], Use TGID, Enable using TGID\n3. TOTI: [13], Trap on TLB instruction?\n4. TGID(renamed from RID): [23:16], TLB GID, relevant to GSTAT.GID. In 3A5000, this value should be identical to GID. However, in 3A6000, these two values may be different.\n\nWhen switching to guest: set TGID = GSTAT.GID; switching to host: set TGID = 0.\n\nIn KVM, [VPID vs VMID](https://lore.kernel.org/all/CAAhV-H51vjwuUgS-GEkMbDs+JAdmT0i3vd13RwuvYju=GwELFw@mail.gmail.com/):\n\n\u003e For processor 3A5000 vpid is the same with vmid, with next generation processor\n\u003e like 3A6000, it is seperated. vpid is for vcpu specific and represents\n\u003e translation from gva to gpa; vmid is the whole vm and represents translation\n\u003e from gpa to hpa, all vcpus shares the same vmid, so that tlb indexed with vpid\n\u003e will be still in effective when flushing shadow tlbs indexed with vmid.\n\u003e\n\u003e Only that VM patch for 3A6000 is not submitted now, generation method for\n\u003e vpid and vmid will be much different. It is prepared for future processor\n\u003e update :)\n\n### TRGP (0x16, TLBR read guest info)(COMPLETELY Inferred)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. GTLB: [0]: Search in GTLB(GVA to GPA) or HTLB(GPA to HPA)?\n2. RID: [23:16]: TGID to match?\n\nControl the TGID and part of TLB for GTLB instructions to operate on.\n\nunused in kernel\n\n### GSTAT (0x50, Guest status)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. VM: [0], In Virtual Machine\n2. PVM: [1], Previous VM, for ERTN PVM=1 means to enter VM, Set PVM bit to setup ertn to guest context, Disable PGM bit to enter root mode by default with next ertn\n3. GIDBIT: [9:4], The number of hardware supported bits of GID\n2. GID: [23:16], Guest ID, correspond to VPID(Virtual Processor ID) in KVM\n\n### GCFG (0x51, Guest config)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.7-rc1)\n\n字段：\n\n1. MATP_GUEST: [0], Memory Access Type?\n2. MATP_ROOT: [1], Memory Access Type?\n3. MATP_NEST: [2], Memory Access Type?\n4. MATC: [5:4], 0=GUEST, 1=ROOT(Control guest page CCA attribute), 2=NEST\n5. SITP: [6], Software Interrupt Trap Pending\n6. SIT: [7], Software Interrupt Trap\n7. TITP: [8], Trap on timer Pending\n8. TIT: [9], Trap on timer, Disable guest use of hard timer\n9. TOEP: [10], Trap on exception Pending\n10. TOE: [11], Trap on exception\n11. TOPP: [12], Trap on privilege Pending\n12. TOP: [13], Trap on privilege\n13. TORUP: [14], Trap on root unimplemented Pending\n14. TORU: [15], Trap on root unimplemented\n15. GCIP: [19:16], Guest Cache Instruction Pending, 0bxxx1=ALL, 0bxx1x=HIT, 0bx1xx=SECURE\n16. GCI: [21:20], Guest Cache Instruction, 0=ALL, 1=HIT, 2=SECURE(Trap on init or unimplemented cache instruction)\n17. GPERF: [26:24], Guest performance counter\n\n\n### GINTC (0x52, Guest interrupt control)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6) [MIPS Virtualization Module](https://mips.com/products/architectures/ase/virtualization/)\n\n字段：\n\n1. VIP: [7:0] Virtual Interrupt Pending, write 1 to the bits in this field to inject the corresponding interrupt to the guest and 0 to clear it. See MIPS `GuestCtl2.VIP`.\n2. PIP: [15:8] Pending Interrupt Passthrough, write 1 to the bits in this field to make the corresponding interrupt visible to the guest. See MIPS `GuestCtl0.PIP`.\n3. HC: [23:16] Hardware Clear, set bits in this field to 1 to allow the the corresponding guest interrupt to be cleared by hardware and 0 to allow only manual clearing. See MIPS `GuestCtl2.HC`.\n\n### GCNTC (0x53, Guest timer offset)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6) [MIPS Virtualization Module](https://mips.com/products/architectures/ase/virtualization/)\n\nSee MIPS `GTOffset`.\n\n### IMPCTL1 (0x80, Loongson config1)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. DATAPRE: [0], Data Prefetch\n2. INSTPRE: [1], Instruction Prefetch\n3. STPRE: [3:2], Store Prefetch\n4. RASDIS: [4], Return Address Stack Disable\n5. BRBTDIS: [5]\n6. LLSYNC: [6], LL Synchronize\n7. LIFEP: [7]\n8. STFILL: [8], Store Fill Buffer\n9. AUTO_FLUSHSFB: [9], Auto Flush Store Fill Buffer\n10. ANTI_MISPEC: [10], Anti Mis-speculation\n11. USERCAC: [11], Use Return ? Address Cache\n12. FASTLDQ: [12], Fast LD.Q\n13. DCLRU: [13], Data Cache LRU\n14. VCLRU: [14], Victim Cache LRU\n15. DISVC: [15]\n16. LLEXCL: [16], LL Exclusive\n17. SCRAND: [17], SC Random Latency\n18. SSEN: [18]\n19. MISPEC: [27:20], Mis-speculation\n\n### IMPCTL2 (0x81, Loongson config2)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. MTLB: [0], Multiple page size TLB\n2. STLB: [1], Singluar page size TLB\n3. DTLB: [2], Data TLB\n4. ITLB: [3], Instruction TLB\n5. BTAC: [4], Branch Target Address Cache\n\n### GNMI (0x82)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n### MCSR0 (0xC0, Shadow of CPUCFG0 and CPUCFG1)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG0: [31:0]\n2. CPUCFG1: [63:32]\n\n### MCSR1 (0xC1, Shadow of CPUCFG2 and CPUCFG3)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG2: [31:0]\n2. CPUCFG3: [63:32]\n\n### MCSR2 (0xC2, Shadow of CPUCFG4 and CPUCFG5)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG4: [31:0]\n2. CPUCFG5: [63:32]\n\n### MCSR3 (0xC3, Shadow of CPUCFG6)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG6: [31:0]\n\n### MCSR8 (0xC8, Shadow of CPUCFG16 and CPUCFG17)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG16: [31:0]\n2. CPUCFG17: [63:32]\n\n### MCSR9 (0xC9, Shadow of CPUCFG18 and CPUCFG19)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG18: [31:0]\n2. CPUCFG19: [63:32]\n\n### MCSR10 (0xCA, Shadow of CPUCFG20)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG20: [31:0]\n\n### MCSR24 (0xF0, Shadow of CPUCFG48)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. CPUCFG48: [31:0]\n\n### UCAWIN (0x100-0x109, Uncached accelerate windows)\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n## CPUCFG\n\n### CPUCFG48\n\n来源：[Linux](https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h?h=v6.6)\n\n字段：\n\n1. MCSRLOCK: [0]: MSR Lock\n2. NAPEN: [1]\n3. VFPUCG: [2]\n4. RAMCG: [3]\n\n\n## IOCSR\n\nIOCSR 可以通过 IOCSR 指令读写，也可以通过 MMIO 读写，其中 MMIO 方式的基地址为 0x1fe00000 或者 0x1fe10000，按 CPU 的内部结点号决定。\n\n参考：3A6000 用户手册、Linux `arch/loongarch/include/asm/loongarch.h`。\n\n### 0x0000: Version\n\n字段：\n\n1. Version: [7:0], 0x14(3A6000)\n\n### 0x0008: Features\n\n字段：\n\n1. Temperature: [0], IOCSR[0x428] is available\n2. Node Counter: [1], IOCSR[0x408] is available\n3. MSI(Message Signaled Interrupt): [2]\n4. EXT IOI(External I/O Interrupt): [3]\n5. CSR IPI(Inter Processor Interrupt): [4], Send IPI via per-core CSR\n6. Frequency CSR: [5], Control frequency via per-core CSR\n7. Frequency Scaling: [6]\n8. DVFS V1: [7]\n9. Temperature Sensor: [8]\n10. EIO(External I/O) DECODE: [9]\n11. Flat Mode: [10]\n12. VM: [11]\n13. Frequency Scale 16: [12]\n14. Interrupt Remap: [13]\n15. SE(Secure Element) enabled: [14]\n\n### 0x0010: Vendor\n\n### 0x0020: CPU Name\n\n### 0x0180: Feature Configuration\n\n字段：\n\n1. MC0 Disable Configuration Space: [4]\n2. MC0 Default Configuration Space: [5], Route all memory access to configuration space\n3. MC0 Reset Negative: [7]\n4. MC0 Clock Enable: [8]\n5. MC1 Disable Configuration Space: [9]\n6. MC1 Default Configuration Space: [10], Route all memory access to configuration space\n7. MC1 Reset Negative: [12]\n8. MC1 Clock Enable: [13]\n9. HT Frequency Scaling Control: [26:24]\n10. HT Clock Enable: [27]\n11. Node Frequency Control: [42:40]\n12. CPU Version: [63:56]\n\nMC: Memory Controller\nHT: HyperTransport\n\n### 0x0188: Pin Configuration\n\n字段：\n\n1. HT Sideband: [19:16]\n2. I2C: [23:20]\n3. UART: [27:24]\n4. SPI: [31:28]\n5. GPIO: [35:32]\n6. SE UART: [39:36]\n7. SE SPI: [43:40]\n8. SE I2C: [47:44]\n9. SE SCI: [51:48]\n10. SE RNG: [55:52]\n11. SE GPIO: [59:56]\n\nSE: Secure Element\n\n### 0x0199: Config Pin Sampling\n\n字段：\n\n1. Chip Config: [37:32]\n2. System Chip Config: [47:38]\n3. Bad IP Core: [55:48]\n4. Bad IP DDR: [57:56]\n5. Bad IP HT: [61:60]\n\n### 0x0198: Temperature Sampling\n\n字段：\n\n1. Do Test: [20]\n2. Temperature Sensor 0 Overflow: [24]\n3. Temperature Sensor 1 Overflow: [25]\n4. Temperature Sensor 0 Output: [47:32]\n5. Temperature Sensor 1 Output: [63:48]\n\n### 0x01B0: Frequency Configuration\n\n字段：\n\n1. Select PLL for Node Clock: [0]\n2. Allow Software to Set PLL: [2]\n3. Bypass L1 PLL: [3]\n4. Bypass L2 PLL: [4]\n5. Enable VDDA LDO: [8]\n6. Enable VDDO LDO: [9]\n7. L2 Reset Negative: [12]\n8. L2 Clock Output Enable: [13]\n9. L2 Fractional Enable: [15]\n10. L1 PLL Locked: [16]\n11. L2 PLL Locked: [17]\n12. Power Down L1: [19]\n13. Power Down L2: [20]\n14. Select L2 PLL: [22]\n15. L1 PLL Reference Clock Cycles: [31:26]\n16. L1 PLL Loop Cycles: [40:32]\n17. L1 PLL Output Cycles: [47:42]\n18. L2 PLL Reference Clock Cycles: [51:48]\n19. L2 PLL Loop Cycles: [63:54]\n20. L2 PLL Log 2 of Output Cycles: [66:64]\n21. L2 PLL Fractional: [115:96]\n\nPLL Output Frequency: (Input Clock / Reference Clock Cycles * Loop Cycles) / Output Cycles\n\n### 0x01C0: Memory Frequency Configuration\n\n字段：\n\n1. Select Mem PLL Source: [0]\n2. Allow Software to Set Mem PLL: [1]\n3. Bypass Mem PLL: [2]\n4. Memory Clock Division Reset Negative: [3]\n5. Memory Clock Mode: [5:4]\n6. Memory PLL Locked: [6]\n7. Power DOwn Memory PLL: [7]\n8. Mem PLL Reference Clock Cycles: [13:8]\n9. Mem PLL Loop Cycles: [23:14]\n10. Mem PLL Output Cycles: [29:24]\n11. Node Clock Select: [30]\n\n### 0x01D0: Core Frequency Configuration\n\n字段：\n\n1. Core 0 Frequency Control: [2:0]\n2. Core 0 Clock Enable: [3]\n3. Core 1 Frequency Control: [6:4]\n4. Core 1 Clock Enable: [7]\n5. Core 2 Frequency Control: [10:8]\n6. Core 2 Clock Enable: [11]\n7. Core 3 Frequency Control: [14:12]\n8. Core 3 Clock Enable: [15]\n\n### 0x01D8: Core Reset Configuration\n\n字段：\n\n1. Core 0 Pre-Reset Negative: [0]\n2. Core 0 Reset Negative: [1]\n3. Core 1 Pre-Reset Negative: [2]\n4. Core 1 Reset Negative: [3]\n5. Core 2 Pre-Reset Negative: [4]\n6. Core 2 Reset Negative: [5]\n7. Core 3 Pre-Reset Negative: [6]\n8. Core 3 Reset Negative: [7]\n\nReset procedure:\n\n1. Set Reset Negative to Zero\n2. Set Pre-Reset Negative to Zero\n3. Wait for 500us\n4. Set Pre-Reset Negative to One\n5. Set Reset Negative to One\n\n### 0x0200: Shared Cache Lock Window 0 Address\n\n字段：\n\n1. Lock Window 0 Address: [47:0]\n2. Lock Window 0 Valid: [63]\n\n### 0x0208: Shared Cache Lock Window 1 Address\n\n字段：\n\n1. Lock Window 1 Address: [47:0]\n2. Lock Window 1 Valid: [63]\n\n### 0x0210: Shared Cache Lock Window 2 Address\n\n字段：\n\n1. Lock Window 2 Address: [47:0]\n2. Lock Window 2 Valid: [63]\n\n### 0x0218: Shared Cache Lock Window 3 Address\n\n字段：\n\n1. Lock Window 3 Address: [47:0]\n2. Lock Window 3 Valid: [63]\n\n### 0x0240: Shared Cache Lock Window 0 Mask\n\n字段：\n\n1. Lock Window 0 Mask: [47:0]\n\n### 0x0248: Shared Cache Lock Window 1 Mask\n\n字段：\n\n1. Lock Window 1 Mask: [47:0]\n\n### 0x0250: Shared Cache Lock Window 2 Mask\n\n字段：\n\n1. Lock Window 2 Mask: [47:0]\n\n### 0x0258: Shared Cache Lock Window 3 Mask\n\n字段：\n\n1. Lock Window 3 Mask: [47:0]\n\n### 0x0280: Shared Cache Configuration\n\n字段：\n\n1. LRU Enable: [0]\n2. Prefetch Enable: [16]\n3. Prefetch Config: [22:20]\n4. Prefetch Lookahead: [26:24]\n6. SC Stall DIRQ Cycle: [30:28]\n7. MCC Store Fill Enable: [31]\n8. MCC Clean Exclusive Replace: [35]\n9. MCC Clean Shared Replace: [36]\n\n### 0x0400: Routing Configuration\n\n字段：\n\n1. Shared Cache ID Selection: [3:0]\n2. Disable 0x3FF00000: [9]\n3. Shared Cache 1MB size: [14]\n4. MC Enable: [31:30]\n5. Memory Interleave Bit: [37:32]\n6. Memory Interleave Enable: [39]\n7. HT Control: [43:40]\n\n### 0x0408: Node Counter\n\n### 0x0420: Other Configuration\n\n字段：\n\n1. Disable JTAG: [0]\n2. Disable Core JTAG: [1]\n3. Disable LA132: [2]\n4. Disable LA132 JTAG: [3]\n5. Disable Anti Fuse 0: [4]\n6. Disable Anti Fuse 1: [5]\n7. Disable ID Modification: [6]\n8. LA132 Reset Negative: [8]\n9. LA132 Sleeping: [9]\n10. LA132 Soft Interrupt: [15:10]\n11. LA132 Frequency Scaling: [18:16]\n12. LA132 Clock Enable: [19]\n13. Stable Clock Reset Negative: [21]\n14. Per Core Frequency Scaling: [22]\n15. Per Core Clock Enable: [23]\n16. Configuration Bus Timeout: [27:24]\n17. Software HT Reset Negative: [29:28]\n18. Core Clock Frequency Scaling Mode: [35:32]\n19. Node Clock Frequency Scaling Mode: [36]\n20. LA132 Clock Frequency Scaling Mode: [37]\n21. HT Clock Frequency Scaling Mode: [39:38]\n22. Stable Clock Frequency Scaling Mode: [40]\n23. Stable Clock Frequency Scaling: [46:44]\n24. Stable Clock Enable: [47]\n25. EXT IOI Enable: [48]\n26. Interrupt Decode: [49]\n27. Interrupt Remap Enable: [51]\n28. Temperature Sensor Select: [57:56]\n29. Auto Scaling: [62:60]\n30. Auto Scaling Status: [63]\n\n### 0x0428: Temperature\n\n字段：\n\n1. Temperature: [7:0]\n\n### 0x0438: SRAM Control\n\n字段：\n\n1. SRAM Control: [7:0]\n\n### 0x0460: Fuse 0\n\n### 0x0470: Fuse 1\n\n### 0x0500: GPIO Output Enable\n\n字段：\n\n1. GPIO Output Enable Negative: [31:0]\n2. GPIO Function Enable Negative: [63:32]\n\n### 0x0508: GPIO I/O\n\n字段：\n\n1. GPIO Output: [31:0]\n2. GPIO Input: [63:32]\n\n### 0x0510: GPIO Interrupt\n\n字段：\n\n1. GPIO Interrupt Polarity: [31:0]\n2. GPIO Interrupt Enable: [63:32]\n\n### 0x0600: MC 0 ECC Control\n### 0x0610: MC 0 ECC Counter\n### 0x0618: MC 0 ECC Counter for each CS\n### 0x0620: MC 0 ECC Code\n### 0x0628: MC 0 ECC Address\n### 0x0630: MC 0 ECC Data 0\n### 0x0638: MC 0 ECC Data 1\n### 0x0640: MC 0 ECC Data 2\n### 0x0648: MC 0 ECC Data 3\n### 0x0700: MC 1 ECC Control\n### 0x0710: MC 1 ECC Counter\n### 0x0718: MC 1 ECC Counter for each CS\n### 0x0720: MC 1 ECC Code\n### 0x0728: MC 1 ECC Address\n### 0x0730: MC 1 ECC Data 0\n### 0x0738: MC 1 ECC Data 1\n### 0x0740: MC 1 ECC Data 2\n### 0x0748: MC 1 ECC Data 3\n\n### 0x1000: Core 0 IPI Status\n### 0x1000: Per Core IPI Status\n### 0x1004: Core 0 IPI Enable\n### 0x1004: Per Core IPI Enable\n### 0x1008: Core 0 IPI Set\n### 0x1008: Per Core IPI Set\n### 0x100C: Core 0 IPI Clear\n### 0x100C: Per Core IPI Clear\n### 0x1010: Per Core Interrupt Status Register\n### 0x1020: Core 0 MailBox 0\n### 0x1020: Per Core MailBox 0\n### 0x1028: Core 0 MailBox 1\n### 0x1028: Per Core MailBox 1\n### 0x1030: Core 0 MailBox 2\n### 0x1030: Per Core MailBox 2\n### 0x1038: Core 0 MailBox 3\n### 0x1038: Per Core MailBox 3\n\n### 0x1040: IPI Send\n### 0x1048: MailBox Send\n\n### 0x1050: Per Core Frequency Scaling\n\n字段：\n\n1. Frequency Scaling: [2:0]\n2. Clock Enable: [3]\n3. Frequency Scaling Mode: [4]\n\n### 0x1058: Frequency Send\n\n### 0x1060: Timer Configuration\n\n来源：Linux\n\n### 0x1070: Timer Tick\n\n来源：Linux\n\n### 0x1100: Core 1 IPI Status\n### 0x1104: Core 1 IPI Enable\n### 0x1108: Core 1 IPI Set\n### 0x110C: Core 1 IPI Clear\n### 0x1120: Core 1 MailBox 0\n### 0x1128: Core 1 MailBox 1\n### 0x1130: Core 1 MailBox 2\n### 0x1138: Core 1 MailBox 3\n### 0x1140: External I/O Interrupt Send\n\n### 0x1158: Any Send\n\n### 0x1200: Core 2 IPI Status\n### 0x1204: Core 2 IPI Enable\n### 0x1208: Core 2 IPI Set\n### 0x120C: Core 2 IPI Clear\n### 0x1220: Core 2 MailBox 0\n### 0x1228: Core 2 MailBox 1\n### 0x1230: Core 2 MailBox 2\n### 0x1238: Core 2 MailBox 3\n\n### 0x1280: ECC Enable\n\n### 0x1300: Core 3 IPI Status\n### 0x1304: Core 3 IPI Enable\n### 0x1308: Core 3 IPI Set\n### 0x130C: Core 3 IPI Clear\n### 0x1320: Core 3 MailBox 0\n### 0x1328: Core 3 MailBox 1\n### 0x1330: Core 3 MailBox 2\n### 0x1338: Core 3 MailBox 3\n\n### 0x1420: Interrupt Status Register\n### 0x1424: Interrupt Enable Register\n### 0x1428: Interrupt Enable Set\n### 0x142c: Interrupt Enable Clear\n### 0x1434: Interrupt Edge\n### 0x1440: Interrupt Status Register for Core 0\n### 0x1448: Interrupt Status Register for Core 1\n### 0x1450: Interrupt Status Register for Core 2\n### 0x1458: Interrupt Status Register for Core 3\n\n### 0x1460: High Temperature Interrupt Control\n### 0x1468: Low Temperature Interrupt Control\n### 0x1470: Temperature Interrupt Status/Clear\n### 0x1478: Temperature Interrupt High\n### 0x1480: Temperature Frequency Scaling\n### 0x1490: Temperature Frequency Scaling High\n### 0x1498: Temperature Control\n\n### 0x14A0-0x14BE: External I/O Node Type\n\n### 0x14C0: External I/O Interrupt Mapping [31:0]\n### 0x14C1: External I/O Interrupt Mapping [63:32]\n### 0x14C2: External I/O Interrupt Mapping [95:64]\n### 0x14C3: External I/O Interrupt Mapping [127:96]\n### 0x14C4: External I/O Interrupt Mapping [159:128]\n### 0x14C5: External I/O Interrupt Mapping [191:160]\n### 0x14C6: External I/O Interrupt Mapping [223:192]\n### 0x14C7: External I/O Interrupt Mapping [255:224]\n\n### 0x1580: Temperature Sensor 0 Control\n### 0x1588: Temperature Sensor 0 Data\n### 0x1590: Temperature Sensor 1 Control\n### 0x1598: Temperature Sensor 1 Data\n\n### 0x1600: External I/O Interrupt Enable [63:0]\n### 0x1608: External I/O Interrupt Enable [127:64]\n### 0x1610: External I/O Interrupt Enable [191:128]\n### 0x1618: External I/O Interrupt Enable [255:192]\n\n### 0x1680: External I/O Interrupt Bounce [63:0]\n### 0x1688: External I/O Interrupt Bounce [127:64]\n### 0x1690: External I/O Interrupt Bounce [191:128]\n### 0x1698: External I/O Interrupt Bounce [255:192]\n\n### 0x1700: External I/O Interrupt Status Register [63:0]\n### 0x1708: External I/O Interrupt Status Register [127:64]\n### 0x1710: External I/O Interrupt Status Register [191:128]\n### 0x1718: External I/O Interrupt Status Register [255:192]\n\n### 0x1800: External I/O Interrupt Status Register for Core 0 [63:0]\n### 0x1800: External I/O Interrupt Status Register Per Core [63:0]\n### 0x1808: External I/O Interrupt Status Register for Core 0 [127:64]\n### 0x1808: External I/O Interrupt Status Register Per Core [127:64]\n### 0x1810: External I/O Interrupt Status Register for Core 0 [191:128]\n### 0x1810: External I/O Interrupt Status Register Per Core [191:128]\n### 0x1818: External I/O Interrupt Status Register for Core 0 [255:192]\n### 0x1818: External I/O Interrupt Status Register Per Core [255:192]\n\n### 0x1900: External I/O Interrupt Status Register for Core 1 [63:0]\n### 0x1908: External I/O Interrupt Status Register for Core 1 [127:64]\n### 0x1910: External I/O Interrupt Status Register for Core 1 [191:128]\n### 0x1918: External I/O Interrupt Status Register for Core 1 [255:192]\n\n### 0x1A00: External I/O Interrupt Status Register for Core 2 [63:0]\n### 0x1A08: External I/O Interrupt Status Register for Core 2 [127:64]\n### 0x1A10: External I/O Interrupt Status Register for Core 2 [191:128]\n### 0x1A18: External I/O Interrupt Status Register for Core 2 [255:192]\n\n### 0x1B00: External I/O Interrupt Status Register for Core 3 [63:0]\n### 0x1B08: External I/O Interrupt Status Register for Core 3 [127:64]\n### 0x1B10: External I/O Interrupt Status Register for Core 3 [191:128]\n### 0x1B18: External I/O Interrupt Status Register for Core 3 [255:192]\n\n### 0x1C00 - 0x1CFF: External I/O Interrupt Mapping for Cores","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjiegec%2Floongarch-csr","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjiegec%2Floongarch-csr","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjiegec%2Floongarch-csr/lists"}