{"id":17774637,"url":"https://github.com/jiegec/ripes","last_synced_at":"2025-08-01T20:02:54.518Z","repository":{"id":68570716,"uuid":"205307863","full_name":"jiegec/Ripes","owner":"jiegec","description":"A fork of https://github.com/mortbopet/Ripes","archived":false,"fork":false,"pushed_at":"2019-10-16T11:35:10.000Z","size":1782,"stargazers_count":4,"open_issues_count":0,"forks_count":0,"subscribers_count":7,"default_branch":"master","last_synced_at":"2025-07-30T21:42:56.838Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jiegec.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-08-30T05:02:05.000Z","updated_at":"2023-12-26T02:22:55.000Z","dependencies_parsed_at":"2023-03-22T14:33:13.128Z","dependency_job_id":null,"html_url":"https://github.com/jiegec/Ripes","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/jiegec/Ripes","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2FRipes","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2FRipes/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2FRipes/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2FRipes/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jiegec","download_url":"https://codeload.github.com/jiegec/Ripes/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2FRipes/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":268290460,"owners_count":24226640,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-08-01T02:00:08.611Z","response_time":67,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-26T21:51:47.494Z","updated_at":"2025-08-01T20:02:54.434Z","avatar_url":"https://github.com/jiegec.png","language":"C++","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Ripes\n[![Build Status](https://travis-ci.org/mortbopet/Ripes.svg?branch=master)](https://travis-ci.org/mortbopet/Ripes/)\n\nRipes is a graphical 5-stage processor pipeline simulator and assembly code editor built for the [RISC-V instruction set architecture](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf), suitable for teaching how assembly level code is executed on a classic pipelined architecture. Ripes is especially suitable for illustrating how concepts such as forwarding and stalling works, giving a visual representation of both cases.\n\u003cp align=\"center\"\u003e\n    \u003cimg src=\"https://github.com/mortbopet/Ripes/blob/master/resources/animation.gif?raw=true\" /\u003e\n\u003c/p\u003e\n\n- [Ripes](#ripes)\n  - [Features](#features)\n  - [Contributing](#contributing)\n  - [Downloading \u0026 Installation](#downloading--installation)\n    - [Linux](#linux)\n    - [Windows](#windows)\n    - [Mac/OSX](#macosx)\n  - [Usage](#usage)\n    - [Editor](#editor)\n    - [Processor](#processor)\n    - [Pipelining table](#pipelining-table)\n    - [Memory](#memory)\n  - [Building](#building)\n\n## Features\n* **Simulator**:\n  * 5-stage graphical pipeline simulator with visualization for multiplexer input selection, register write/enable signals and more.\n  * Stage information: Current stage instructions are displayed above each stage, as well as in the instruction memory view\n  * Breakpoint setting\n  * Supports RISC-V assembly files \u0026 RISC-V binary files (extracted *.text* segments) - supported instructions are the **RV32I** Base Instruction Set as well as **RV32M** Standard Extension.\n* **Memory**:\n  * Display type selection for various display formats (Hex, Decimal, ...)\n  * Memory view with features such as scrolling adress saving and adress jumping\n* **Editor**:\n  * Syntax highlighting and syntax error information\n  * Real-time assembler for side-by-side comparison of assembly code and (disassembled) binary code\n\n## Contributing\nCurrently, Ripes features a single processor model - a 5 stage pipeline. However, in learning about computer architecture it may be valuable to have access to both less and more complex processor models.  \nA future goal for Ripes is to contain processor models such as the following:\n* Single-cycle\n* 2/3 stage pipeline\n* 5 stage pipeline without forwarding/hazard detection\n* 5 stage pipeline with forwarding/hazard detection\n* 5 stage pipeline(s) with varying placements of branching logic\n\nHowever, describing all of these models with method of implementation currently used in Ripes would be highly tedious.\n\nInstead, [VSRTL](https://github.com/mortbopet/VSRTL) was created. VSRTL is intended to be a collection of libraries and applications for visualizing simulations of digital circuits. VSRTL is currently in active development, and when mature, may be used to describe an arbitrary number of processor models for Ripes.  \nVSRTL is in active development and looking for developers - if this sounds interesting, check out the [documentation](https://github.com/mortbopet/VSRTL/tree/master/docs) or current [issues](https://github.com/mortbopet/VSRTL/issues) for further info.\n\n\n## Downloading \u0026 Installation\nPrebuilt applications are available for Linux, Windows \u0026 Mac/OSX. No installation is required - all required libraries are packaged with the compiled executable - these are available at the [Releases page](https://github.com/mortbopet/Ripes/releases).  \n**It is recommended to use the *continuous releases*, since they contain all of the most-recent bug-fixes.**\n\n### Linux\nReleases for Linux are distributed in the AppImage format. To run an AppImage:\n* Run `chmod a+x` on the AppImage file\n* Run the file!\nThe AppImage for Linux should be compatible with most Linux distributions.\n\n### Windows\nFor Windows, the C++ runtime library must be available (if not, a msvcp140.dll error will be produced). You most likely already have this installed, but if this is not the case, you download it [here](https://www.microsoft.com/en-us/download/details.aspx?id=48145).\n\n### Mac/OSX\nPlease note that the Mac/OSX is *mostly untested* and as such, there may be various visual glitches as well as performance issues.\n\n## Usage\nThe [Ripes wiki](https://github.com/mortbopet/Ripes/wiki) contains various pages relating to writing RISC-V assembly code, as well as a list of the supported simulator features in terms of assembler directives etc.  \nTo simulate C/C++ code in Ripes, [Matt Godbolt's](https://github.com/mattgodbolt) [Compiler Explorer](https://godbolt.org/) is a fast and easy-to-use web-based tool for generating RISC-V assembly code from C/C++. With minor modifications, the output from Compiler Explorer can be inserted into Ripes and simulated. For instructions on how to run code generated by Compiler Explorer, [refer to this wiki page](https://github.com/mortbopet/Ripes/wiki/Adapting-Compiler-Explorer-generated-RISC-V-assembly-code).\n\n### Editor\nGet started by selecting one of the assembly examples through *File-\u003eLoad Example-\u003eassembly*. In the **Editor** tab, you should now see that some RISC-V assembly code is present in the left view.\nTry changing some values or adding more instructions - you should see that the right side will change accordingly. By default, this view shows the disassembled version of the binary instructions that the left view has been assembled into.\nIf you want to view the raw binary information, select *Binary* as *View mode*.\n\n\u003cp align=\"center\"\u003e\n    \u003cimg src=\"https://github.com/mortbopet/Ripes/blob/master/resources/asmeditorpng.png?raw=true\"/\u003e\n\u003c/p\u003e\n\n### Processor\nOnce no syntax errors have been found in your assembly code, your code will automatically be assembled and loaded into the simulator.\nSwitching to the **Processor** tab, you'll be greeted by a datapath picturing a classic 5-stage RISC pipeline architecture. Note that a *Control* component nor most control signals aren't included in the view. This descision has been made to reduce clutter. All control signals are generated in the ID (Instruction decode) stage, and are propagated through the stage-separating registers accordingly.\n\n\u003cp align=\"center\"\u003e\n    \u003cimg src=\"https://github.com/mortbopet/Ripes/blob/master/resources/processortab.png?raw=true\"/\u003e\n\u003c/p\u003e\n\nBesides the datapath, this tab contains the following elements:\n* Simulator control:\n    * **(1) Run** will run the program until a breakpoint is encountered or execution is finished. This will postpone updating the visualized datapath until the break is encountered.\n    * **(2) Autostepping** will automatically step through the program with a speed determined by the execution speed slider **(5)**. \n    * **(3) Step** is equal to activating the clock signal in the circuit. This will clock next-state signals into the registers, and new signals are calculated (propagate through the circuit)\n    * **(4) Reset** resets the simulator, resetting all stages and setting the program counter to point to the first instruction\n* **(6) Display all signal values** will show the underlying output signals for most signals in the datapath\n* **(7) Pipeline table**: see below\n* **(8)** Various buttons are available for zooming \u0026 expanding the datapath view\n* **(9) Registers** is a view of the value of all registers in the processor, with highlighting for the most-recently used register\n* **(10) Instruction memory**: A view of the disassembled instructions that are currently loaded in the processor. This view displays which instructions are present in each pipeline stage, as well as breakpoint setting functionality\nFurthermore, the following options are available:\n\n### Pipelining table \n\u003cp align=\"center\"\u003e\n    \u003cimg src=\"https://github.com/mortbopet/Ripes/blob/master/resources/ptable.PNG?raw=true\"/\u003e\n\u003c/p\u003e\nwill display a pop-up window with the stage information for the current program. The program must be run to propagate the chart. The pipeline table can be copied and pasted to spreadsheets.\n\n### Memory\nSelecting the **Memory** tab will show you three different views:\n* Registers - similar to the view presented in the processor tab\n* A memory view, where all parts of the program memory can be inspected. To navigate, one can use the scroll view or select one of the predefined destinations (or to a specific address) via the *Go to* combobox. A label for an address can be saved for future use, via. the *Save address* button. \n* A list of the most recent memory accesses. Selecting an entry and pressing *Go to selected address* sets the right side memory view to center at the address for the given entry\n\n\u003cp align=\"center\"\u003e\n    \u003cimg src=\"https://github.com/mortbopet/Ripes/blob/master/resources/memorytab.png?raw=true\"/\u003e\n\u003c/p\u003e\n\n## Building\nSince Ripes is built using pure C++ and Qt, all platforms that support Qt should be able to build and run the app.\nRipes contains no external dependencies and (Assuming you have a Qt environment in your PATH) can be built by the following commands:\n```\nUnix:               Windows:\ncd Ripes/           cd Ripes/\nqmake               qmake.exe\nmake                jom.exe\n```\nDownload Qt for Open Source development at https://www.qt.io/download.\nUsing the Qt installer, only the prebuilt components for your chosen compiler needs to be selected.\n\n---\nIcons kindly provided by Flaticon authors: [Smashicons](https://www.flaticon.com/authors/smashicons), [Freepik](https://www.flaticon.com/authors/freepik), [Vectors Market](https://www.flaticon.com/authors/vectors-market) \u0026 [Pixel Buddha](https://www.flaticon.com/authors/pixel-buddha).\n\n\u003ca href=\"https://www.qt.io/\"\u003e\n    \u003cimg src=\"https://github.com/mortbopet/Ripes/blob/master/resources/QtIcon.png\" width=\"60\" height=\"60\" /\u003e\n\u003c/a\u003e\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjiegec%2Fripes","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjiegec%2Fripes","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjiegec%2Fripes/lists"}