{"id":13649167,"url":"https://github.com/jiegec/rocket-chip-vcu128","last_synced_at":"2025-04-01T15:33:16.822Z","repository":{"id":68570802,"uuid":"411171510","full_name":"jiegec/rocket-chip-vcu128","owner":"jiegec","description":"Run Rocket Chip on VCU128","archived":false,"fork":false,"pushed_at":"2024-11-27T12:43:25.000Z","size":149,"stargazers_count":29,"open_issues_count":0,"forks_count":4,"subscribers_count":3,"default_branch":"master","last_synced_at":"2025-02-07T09:45:41.670Z","etag":null,"topics":["risc-v","rocket-chip","vcu128"],"latest_commit_sha":null,"homepage":"","language":"Tcl","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jiegec.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-09-28T07:01:01.000Z","updated_at":"2024-12-05T14:25:23.000Z","dependencies_parsed_at":null,"dependency_job_id":"6f6efdb3-bc30-496b-a0b4-008c8e975906","html_url":"https://github.com/jiegec/rocket-chip-vcu128","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Frocket-chip-vcu128","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Frocket-chip-vcu128/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Frocket-chip-vcu128/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jiegec%2Frocket-chip-vcu128/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jiegec","download_url":"https://codeload.github.com/jiegec/rocket-chip-vcu128/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246662665,"owners_count":20813775,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["risc-v","rocket-chip","vcu128"],"created_at":"2024-08-02T01:04:49.031Z","updated_at":"2025-04-01T15:33:16.802Z","avatar_url":"https://github.com/jiegec.png","language":"Tcl","funding_links":[],"categories":["Tcl"],"sub_categories":[],"readme":"# rocket-chip-vcu128\n\nPort Rocket Chip to VCU128 platform. Based on [rocket2thinpad](https://github.com/jiegec/rocket2thinpad). Tested with Vivado 2020.2.\n\nCAVEAT: You can use either BOOM Core or Rocket Core. Change configuration at `src/main/scala/Configs.scala` before building.\n\nAXI Interconnect memory mapping:\n\n1. AXI Quad SPI: 0x6010_0000\n2. AXI UART16550: 0x6020_0000\n3. AXI Ethernet DMA: 0x6030_0000\n4. AXI Ethernet: 0x6040_0000\n5. AXI I2C: 0x6050_0000\n6. HBM: 0x8000_0000 ~ 0x9FFF_FFFF\n\nRocket Chip memory mapping:\n\n1. Boot ROM: 0x0001_0000\n2. CLINT: 0x0200_0000\n3. MMIO: 0x6000_0000 ~ 0x7FFF_FFFF\n4. Memory: 0x8000_0000 ~ 0xFFFF_FFFF\n\nExternal interrupt:\n\n1. AXI UART16550\n2. AXI Quad SPI\n3. AXI Ethernet\n4. AXI Ethernet DMA RX\n5. AXI Ethernet DMA TX\n6. AXI I2C\n\nAccess uart from USB at /dev/ttyUSB2, baudrate 115200. A virtual reset is available at VIO.\n\nSoftware modifications:\n\n- [Custom OpenSBI](https://github.com/jiegec/opensbi/tree/rocket-chip-vcu128) [Changes](https://github.com/jiegec/opensbi/compare/master...jiegec:opensbi:rocket-chip-vcu128?expand=1)\n- [Custom U-Boot](https://github.com/jiegec/u-boot/tree/rocket-chip-vcu128) [Changes](https://github.com/jiegec/u-boot/compare/master...jiegec:u-boot:rocket-chip-vcu128?expand=1)\n- [Custom Linux](https://github.com/jiegec/linux/tree/rocket-chip-vcu128) [Changes](https://github.com/jiegec/linux/compare/master...jiegec:linux:rocket-chip-vcu128?expand=1)\n- [Custom Buildroot](https://github.com/jiegec/buildroot/tree/rocket-chip-vcu128)\n- [Custom Buildroot External](https://github.com/jiegec/buildroot-external/tree/master/rocket-chip-vcu128)\n\nBoot custom OpenSBI in M-mode with custom U-Boot in S-mode:\n\n```shell\n# place custom opensbi at ~/opensbi, custom uboot at ~/u-boot\n# in u-boot\n$ ./build.sh\n# in this repo\n$ python3 boot.py ~/opensbi/build/platform/rocket-chip-vcu128-dual-core/firmware/fw_payload.bin /dev/ttyUSB2\nBoot HART ID              : 1\nBoot HART Domain          : root\nBoot HART Priv Version    : v1.11\nBoot HART Base ISA        : rv64imafdcx\nBoot HART ISA Extensions  : sdtrig\nBoot HART PMP Count       : 8\nBoot HART PMP Granularity : 2 bits\nBoot HART PMP Address Bits: 30\nBoot HART MHPM Info       : 0 (0x00000000)\nBoot HART Debug Triggers  : 1 triggers\nBoot HART MIDELEG         : 0x0000000000000222\nBoot HART MEDELEG         : 0x000000000000b109\n\n\nU-Boot 2024.10-g33523922a4ac (Nov 16 2024 - 11:29:29 +0800)\n\nCPU:   sifive,rocket0\nModel: freechips,rocketchip-unknown\nDRAM:  512 MiB\nCore:  16 devices, 12 uclasses, devicetree: board\nLoading Environment from nowhere... OK\nIn:    serial@60200000\nOut:   serial@60200000\nErr:   serial@60200000\nNet:   AXI EMAC: 60400000, phyaddr 3, interface sgmii\neth0: eth0@60400000\n=\u003e\n```\n\nRun bare-metal executable from TFTP:\n\n```shell\n# build and launch tftp server\n$ sudo pip3 install -U py3tftp\n$ cd software\n$ make\n$ sudo python3 -m py3tftp -p 69\n# in u-boot\n=\u003e tftpboot 0x80200000 10.0.0.1:uart.img\nUsing eth0@60400000 device\nTFTP from server 10.0.0.1; our IP address is 10.0.0.2\nFilename 'uart.img'.\nLoad address: 0x80200000\nLoading: #\n         929.7 KiB/s\ndone\nBytes transferred = 952 (3b8 hex)\n=\u003e go 0x80200000\n## Starting application at 0x80200000 ...\ntest\n```\n\nBoot custom Linux with custom [Buildroot external repo](https://github.com/jiegec/buildroot-external/tree/master/rocket-chip-vcu128):\n\n```shell\n# in buildroot-external\n$ cd rocket-chip-vcu128\n$ ./build.sh\n# in linux\n$ ./build.sh\n# in this repo\n$ python3 boot.py ~/opensbi/build/platform/rocket-chip-vcu128-dual-core/firmware/fw_payload.bin /dev/ttyUSB2\n=\u003e run boot_dual\nUsing eth0@60400000 device\nTFTP from server 10.0.0.1; our IP address is 10.0.0.2\nFilename 'image.itb'.\nLoad address: 0x80100000\n[    1.757872] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\n[    1.778840] printk: console [ttyS0] disabled\n[    1.782014] 60200000.serial: ttyS0 at MMIO 0x60201000 (irq = 1, base_baud = 6250000) is a 16550A\n[    1.787402] printk: console [ttyS0] enabled\n[    1.787402] printk: console [ttyS0] enabled\n[    1.792138] printk: bootconsole [sbi0] disabled\n[    1.792138] printk: bootconsole [sbi0] disabled\n\n[    1.847546] Freeing unused kernel image (initmem) memory: 2116K\n[    1.851446] Run /init as init process\nStarting syslogd: OK\nStarting klogd: OK\nRunning sysctl: OK\n\nWelcome to Buildroot\nbuildroot login: root\nJan  1 00:00:28 login[82]: root login on 'ttyS0'\n```\n\nLaunch OpenOCD \u0026 GDB for debugging:\n\n```shell\n$ openocd -f openocd.cfg\nOpen On-Chip Debugger 0.12.0\nLicensed under GNU GPL v2\nFor bug reports, read\n        http://openocd.org/doc/doxygen/bugs.html\n1\nInfo : Listening on port 6666 for tcl connections\nInfo : Listening on port 4444 for telnet connections\nInfo : clock speed 10000 kHz\nInfo : JTAG tap: riscv.cpu tap/device found: 0x10000913 (mfg: 0x489 (SiFive Inc), part: 0x0000, ver: 0x1)\nInfo : datacount=2 progbufsize=16\nInfo : Disabling abstract command reads from CSRs.\nInfo : Examined RISC-V core; found 2 harts\nInfo :  hart 0: XLEN=64, misa=0x800000000094112d\nInfo : starting gdb server for riscv.cpu.0 on 3333\nInfo : Listening on port 3333 for gdb connections\n$ riscv64-unknown-elf-gdb\nGNU gdb (GDB) 12.0.50.20220308-git\nCopyright (C) 2022 Free Software Foundation, Inc.\nLicense GPLv3+: GNU GPL version 3 or later \u003chttp://gnu.org/licenses/gpl.html\u003e\nThis is free software: you are free to change and redistribute it.\nThere is NO WARRANTY, to the extent permitted by law.\nType \"show copying\" and \"show warranty\" for details.\nThis GDB was configured as \"--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf\".\nType \"show configuration\" for configuration details.\nFor bug reporting instructions, please see:\n\u003chttps://www.gnu.org/software/gdb/bugs/\u003e.\nFind the GDB manual and other documentation resources online at:\n    \u003chttp://www.gnu.org/software/gdb/documentation/\u003e.\n\nFor help, type \"help\".\nType \"apropos word\" to search for commands related to \"word\".\n(gdb) target extended-remote localhost:3333\nRemote debugging using localhost:3333\nwarning: No executable has been specified and target does not support\ndetermining executable automatically.  Try using the \"file\" command.\n0x0000000000010106 in ?? ()\n(gdb) \n```\n\nBoot process:\n\n1. Run BootROM in 0x10000, load opensbi+uboot from serial\n2. Run OpenSBI @ 0x80000000, jump to U-Boot at 0x80040000\n3. U-Boot relocates to high address, load Linux kernel + dts from network at 0x80100000\n4. Copy Linux kernel to 0x82000000 and jump to Linux kernel\n\nPerformance of one big Rocket Chip running Linux @ 50MHz:\n\n- Dhrystone(-O2): 122850.1 per second, `122850.1 / 1757 / 50 = 1.40 DMIPS/MHz`\n- Coremark(-O2): 104.2 per second, `104.2 / 50 = 2.08 Coremark/MHz`\n- Whetstone: 33.3 MIPS\n\nPerformance of one medium BOOM core running Linux @ 50MHz:\n\n- Dhrystone(-O2): 197238.7 per second, `197238.7 / 1757 / 50 = 2.25 DMIPS/MHz`\n- Coremark(-O2): 171.0 per second, `171.0 / 50 = 3.42 Coremark/MHz`\n- Whetstone: 50.0/100.0 MIPS\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjiegec%2Frocket-chip-vcu128","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjiegec%2Frocket-chip-vcu128","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjiegec%2Frocket-chip-vcu128/lists"}