{"id":13783162,"url":"https://github.com/jjunac/InterpreterAsm","last_synced_at":"2025-05-11T17:31:14.267Z","repository":{"id":67562706,"uuid":"75278916","full_name":"jjunac/InterpreterAsm","owner":"jjunac","description":"Compile ASM files into file that can be interpreted byt the microprocessor built during the \"Program Execution\" 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Utilisation\n\nTransforme les fichiers ASM en fichier qui peuvent etre ouvert par le micro-processeur.\n  \n```batch\nInterpreteurAsm.exe src dst\n```\n\n# Instructions ARM\n\n\n* \\#0: an immediate value to be used by the operation\n* Rd: destination register\n* Rm: register that contains the first operande\n* Rn: register that contains the second operande (also destination register when 'Rdn')\n\n\n### Data Processing\n\n\nOP |Instruction\t\t\t\t|OPTYPE|OPCODE\t|XXX|XXX|Encoding\n---|------------------------|------|--------|---|---|--------\nAND|Bitwise AND\t\t\t\t|010000|0000\t|Rm |Rdn|AND \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nEOR|Exclusive OR\t\t\t|010000|0001\t|Rm |Rdn|EOR \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nLSL|Logical Shift Left\t\t|010000|0010\t|Rm |Rdn|LSL \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nLSR|Logical Shift Right\t\t|010000|0011\t|Rm |Rdn|LSR \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nASR|Arithmetic Shift Right\t|010000|0100\t|Rm |Rdn|ASR \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nADC|Add with Carry\t\t\t|010000|0101\t|Rm |Rdn|ADC \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nSBC|Substract with Carry\t|010000|0110\t|Rm |Rdn|SBC \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nROR|Rotate Right\t\t\t|010000|0111\t|Rm |Rdn|ROR \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nTST|Test\t\t\t\t\t|010000|1000\t|Rm |Rn |TST \\\u003cRn\\\u003e,\\\u003cRm\\\u003e\nRSB|Reverse Substract\t\t|010000|1001\t|Rn |Rd |RSB \\\u003cRd\\\u003e,\\\u003cRn\\\u003e,\\#0\nCMP|Compare Registers\t\t|010000|1010\t|Rm |Rn |CMP \\\u003cRn\\\u003e,\\\u003cRm\\\u003e\nCMN|Compare Negative\t\t|010000|1011\t|Rm |Rn |CMN \\\u003cRn\\\u003e,\\\u003cRm\\\u003e\nORR|Logical OR\t\t\t\t|010000|1100\t|Rm |Rdn|ORR \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nMUL|Multiply\t\t\t\t|010000|1101\t|Rn |Rdm|MUL \\\u003cRdm\\\u003e,\\\u003cRn\\\u003e,\\\u003cRdm\\\u003e\nBIC|Bit Clear\t\t\t\t|010000|1110\t|Rm |Rdn|BIC \\\u003cRdn\\\u003e,\\\u003cRm\\\u003e\nMVN|Bitwise NOT\t\t\t\t|010000|1111\t|Rm |Rd |MVN \\\u003cRd\\\u003e,\\\u003cRm\\\u003e\n\n\n### Shift, add, sub, move\n\n\nOP\t|Instruction\t\t\t\t\t\t|XXX\t|XX\t|XX\t\t|X\t\t|XX\t\t|XXX|XXX|Encoding\n----|-----------------------------------|-------|---|-------|-------|-------|---|---|--------\nLSL\t|Logical Shift Left (immediate)\t\t|000\t|00\t|\\#imm5\t|_\t\t|_\t\t|Rm |Rd |LSL \\\u003cRd\\\u003e,\\\u003cRm\\\u003e,\\#imm5\nLSR\t|Logical Shift Right (immediate)\t|000\t|01\t|\\#imm5\t|_\t\t|_\t\t|Rm |Rd |LSR \\\u003cRd\\\u003e,\\\u003cRm\\\u003e,\\#imm5\nASR\t|Arithmetic Shift Right (immediate)\t|000\t|10\t|\\#imm5\t|_\t\t|_\t\t|Rm |Rd |ASR \\\u003cRd\\\u003e,\\\u003cRm\\\u003e,\\#imm5\nADD\t|Add (register)\t\t\t\t\t\t|000\t|11\t|00\t\t|Rm\t\t|_\t\t|Rn |Rd |ADD \\\u003cRd\\\u003e,\\\u003cRn\\\u003e,\\\u003cRm\\\u003e\nSUB\t|Substract (register)\t\t\t\t|000\t|11\t|01\t\t|Rm\t\t|_\t\t|Rn |Rd |SUB \\\u003cRd\\\u003e,\\\u003cRn\\\u003e,\\\u003cRm\\\u003e\nMOV\t|Move (immediate)\t\t\t\t\t|001\t|00\t|Rd\t\t|_\t\t|\\#imm8\t|_\t|_\t|MOV \\\u003cRd\\\u003e,\\#imm8\n\n\n### Load, Store\n\n\nOP |Instruction\t\t\t\t\t|XXXXX|XXXXX\t|XXX|XXX|Encoding\n---|----------------------------|-----|---------|---|---|--------\nSTR|Store Register (immediate)\t|01100|\\#imm5\t|Rn\t|Rt\t|STR \\\u003cRt\\\u003e, \\[\\\u003cRn\\\u003e, \\#imm5\\]\nLDR|Load Register (immediate)\t|01101|\\#imm5\t|Rn |Rt |LDR \\\u003cRt\\\u003e, \\[\\\u003cRn\\\u003e, \\#imm5\\]\n\n\n### Branch\n\n* \u003ccond\u003e cannot be omitted !\n* imm32 = SignExtend(imm8:'0', 32)\n* imm32 is the Program Counter value of the label in the program. imm8 must be encoded to set the correct value for imm32.\n\nOP |Instruction\t|XXXX|XXXX|XXXXXXXX\t|Encoding\n---|------------|----|----|---------|--------\nB  |Branch\t\t|1101|cond|\\#imm8\t|B\\\u003ccond\\\u003e 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