{"id":13958929,"url":"https://github.com/jmahler/mips-cpu","last_synced_at":"2026-03-11T20:31:09.278Z","repository":{"id":8258553,"uuid":"9708149","full_name":"jmahler/mips-cpu","owner":"jmahler","description":"MIPS CPU implemented in Verilog","archived":false,"fork":false,"pushed_at":"2017-10-03T13:18:50.000Z","size":297,"stargazers_count":639,"open_issues_count":1,"forks_count":189,"subscribers_count":44,"default_branch":"master","last_synced_at":"2025-12-20T23:43:57.745Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jmahler.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2013-04-27T02:43:18.000Z","updated_at":"2025-12-19T00:30:26.000Z","dependencies_parsed_at":"2022-08-07T00:00:55.135Z","dependency_job_id":null,"html_url":"https://github.com/jmahler/mips-cpu","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/jmahler/mips-cpu","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jmahler%2Fmips-cpu","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jmahler%2Fmips-cpu/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jmahler%2Fmips-cpu/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jmahler%2Fmips-cpu/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jmahler","download_url":"https://codeload.github.com/jmahler/mips-cpu/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jmahler%2Fmips-cpu/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":30399261,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-11T18:46:22.935Z","status":"ssl_error","status_checked_at":"2026-03-11T18:46:17.045Z","response_time":84,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-08T13:02:07.062Z","updated_at":"2026-03-11T20:31:09.253Z","avatar_url":"https://github.com/jmahler.png","language":"Verilog","funding_links":[],"categories":["CPU RISC-V"],"sub_categories":["网络服务_其他"],"readme":"# NAME\n\nmips-cpu - A MIPS CPU written in Verilog\n\n# DESCRIPTION\n\nAn implementation of a MIPS CPU written in Verilog.  This project is in\nvery early stages and currently only implements the most basic\nfunctionality of a MIPS CPU.\n\n - 32-bit MIPS processor\n\n - implemented in Verilog\n\n - 5 stage pipeline\n\n - static branch not taken branch predictor\n\n - branch detection in decode (stage 2)\n\n - supports stalls to avoid read after write (RAW) and other hazards\n\n - can forward from memory (stage 4) and write back (stage 5)\n   to avoid stalls\n\nMuch of the design was inspired by the book \"Computer Organization and\nDesign\" by David A. Patterson and John L. Hennessy (4th ed. 2008).\n\nThis project also includes a full set of test benches.  These are\ninvaluable as a quick check to verify that new changes have not\ndisrupted previously working functionality.\n\n# REQUIREMENTS\n\nThis project requires a Verilog simulator, such as [Icarus][iverilog],\nthe Gcc compiler, and a Gcc MIPS cross compiler.  To check if your\nsystem has the required programs installed run the `check-install.sh`\nscript.\n\n    $ ./check-install.sh\n    Checking for required programs...\n      mips-linux-gnu-objcopy\n      mips-linux-gnu-as\n      iverilog\n    Please install the missing programs and retry.\n\n  [iverilog]: http://iverilog.icarus.com\n\n# RUNNING TEST BENCHES\n\nThe tests are located in the `verilog/test/` directory.  Everything is\nbuilt and run using the `make` command.\n\n    make\n\nThere are two parts to each test: the Verilog code, and the assembly\ncode.  The Verilog code uses a generic CPU test bench (`cpu_tb.v`) from\nwhich a specific test is built using a specific assembled .hex file.\nThe .hex file is produced by assembling the .asm file using the Gcc MIPS\ncross compiler and converting it to ASCII hex suitable for use with\nVerilog.  Then the Verilog code, using a simulator such as\n[Icarus Verilog][iverilog], can be run to execute the assembly\ninstructions and produce a dump of its output (.out).  Finally, the\noutput file (.out) can be diffed against a known good output file\n(.check) to see if there are any differences.\n\nFor more information about these steps refer the Makefile in `verilog/test/`.\n\n# AUTHOR\n\nJeremiah Mahler \u003cjmmahler@gmail.com\u003e\u003cbr\u003e\n\u003chttp://github.com/jmahler\u003e\n\n# COPYRIGHT\n\nCopyright \u0026copy; 2015, Jeremiah Mahler.  All Rights Reserved.\u003cbr\u003e\nThis project is free software and released under\nthe [GNU General Public License][gpl].\n\n [gpl]: http://www.gnu.org/licenses/gpl.html\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjmahler%2Fmips-cpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjmahler%2Fmips-cpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjmahler%2Fmips-cpu/lists"}