{"id":25753700,"url":"https://github.com/jn513/fpga_basics","last_synced_at":"2026-03-01T21:32:49.340Z","repository":{"id":277080895,"uuid":"931238446","full_name":"JN513/fpga_basics","owner":"JN513","description":"Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog","archived":false,"fork":false,"pushed_at":"2025-02-25T13:06:27.000Z","size":61,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-26T15:19:31.868Z","etag":null,"topics":["basic","fpga","learning","verilog","verilog-hdl","vhdl","vhdl-code"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/JN513.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.md","funding":null,"license":"LICENSE","code_of_conduct":"CODE_OF_CONDUCT.md","threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":"SECURITY.md","support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-02-12T00:07:07.000Z","updated_at":"2025-02-25T13:06:31.000Z","dependencies_parsed_at":"2025-02-12T16:46:16.689Z","dependency_job_id":null,"html_url":"https://github.com/JN513/fpga_basics","commit_stats":null,"previous_names":["jn513/verilog_basics","jn513/fpga_basics"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/JN513/fpga_basics","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JN513%2Ffpga_basics","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JN513%2Ffpga_basics/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JN513%2Ffpga_basics/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JN513%2Ffpga_basics/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/JN513","download_url":"https://codeload.github.com/JN513/fpga_basics/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/JN513%2Ffpga_basics/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":29984724,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-03-01T21:06:37.093Z","status":"ssl_error","status_checked_at":"2026-03-01T21:05:45.052Z","response_time":124,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["basic","fpga","learning","verilog","verilog-hdl","vhdl","vhdl-code"],"created_at":"2025-02-26T15:19:31.644Z","updated_at":"2026-03-01T21:32:49.322Z","avatar_url":"https://github.com/JN513.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Verilog Basics\n\nBasic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog\n\n# Roadmap\n\n0 - blink\n1 - led counter\n2 - led shiffter\n3 - button\n4 - hamming code\n5 - button modes\n6 - semaphore\n7 - 7 segment\n8 - 7 segment semaphore\n9 - simple clock\n10 - sum\n11 - calculator\n\n\n## Project Official Language\n\nThe official language adopted by the project is Brazilian Portuguese; therefore, most of the documentation and commits are in this language.\n\n## Contribution\n\nIf you'd like to contribute to the project, please feel free to do so. The [CONTRIBUTING.md](https://github.com/JN513/verilog_basics/blob/main/CONTRIBUTING.md) file contains the necessary instructions.\n\n## License\n\nThis project is licensed under the [MIT license](https://github.com/JN513verilog-buses-implementations/blob/main/LICENSE), which grants full freedom for use.","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjn513%2Ffpga_basics","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjn513%2Ffpga_basics","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjn513%2Ffpga_basics/lists"}