{"id":18635533,"url":"https://github.com/jonlamb-gh/solox-amp-rust","last_synced_at":"2025-04-11T08:30:36.952Z","repository":{"id":105864294,"uuid":"146185591","full_name":"jonlamb-gh/solox-amp-rust","owner":"jonlamb-gh","description":"AMP experiments in feL4 (seL4/Rust) on SoloX ARM SoC (A9 + M4)","archived":false,"fork":false,"pushed_at":"2018-10-15T13:50:44.000Z","size":82,"stargazers_count":5,"open_issues_count":0,"forks_count":1,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-03-25T11:38:51.184Z","etag":null,"topics":["arm","cortex-a9","cortex-m4","fel4","imx6","no-std","openamp-rpmsg","rust","rust-embedded","sel4"],"latest_commit_sha":null,"homepage":"","language":"Rust","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/jonlamb-gh.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-08-26T14:03:50.000Z","updated_at":"2023-10-06T20:43:28.000Z","dependencies_parsed_at":null,"dependency_job_id":"c85441eb-2cf0-4777-bbbb-b7e954d8fac0","html_url":"https://github.com/jonlamb-gh/solox-amp-rust","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jonlamb-gh%2Fsolox-amp-rust","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jonlamb-gh%2Fsolox-amp-rust/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jonlamb-gh%2Fsolox-amp-rust/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/jonlamb-gh%2Fsolox-amp-rust/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/jonlamb-gh","download_url":"https://codeload.github.com/jonlamb-gh/solox-amp-rust/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248361457,"owners_count":21090903,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["arm","cortex-a9","cortex-m4","fel4","imx6","no-std","openamp-rpmsg","rust","rust-embedded","sel4"],"created_at":"2024-11-07T05:25:28.460Z","updated_at":"2025-04-11T08:30:36.945Z","avatar_url":"https://github.com/jonlamb-gh.png","language":"Rust","readme":"# solox-amp-rust\n\n[AMP][open-amp] experiments in feL4 (seL4/Rust) on SoloX ARM SoC (A9 + M4)\n\nThe [Nitrogen6 SoloX][solox] SoC has both an A9 core and an M4 core.\n\nHere's a good [article][bd-article] that describes the platform.\n\nSee the [TRM][trm] for register details.\n\n## About the project\n\nThe seL4 kernel, root-task and threads run on the A9 core.\n\nA bare metal Rust cortex-m project runs on the M4 core.\n\n- U-boot does initial bootstrapping of the A9 core and loads the master ELF binary\n- seL4 kernel is started on the A9 core\n- seL4 root task initializes some memory, devices and I/O for a thread\n- seL4 thread loads the M4 core firmware from the CPIO archive linked into the master ELF binary\n- seL4 thread starts up the M4 core and clock\n\n## Building\n\n**NOTE**: requires a cargo-fel4 that does not overwrite the `src/bin/root-task.rs` file\n\nHere's a [branch](https://github.com/jonlamb-gh/cargo-fel4/tree/keep-root-rask-for-development) I use.\n\nNote that the L2 cache memory is currently defined as OCRAM for the M4 core.\n\nModify U-boot environment:\n\n```bash\n# default loadaddr\nloadaddr=0x82000000\n\n# move it up a bit so we don't overlap with the elf-loader, Rust binaries are big right now\nsetenv loadaddr 0x83000000\n\n# boot alias command\nsetenv bootfel4img 'tftp ${loadaddr} ${serverip}:feL4img; dcache flush; dcache off; go ${loadaddr}'\n```\n\nApply local patches to convert the imx6/sabre-lite platform into something the SoloX will run.\n\n```bash\n./scripts/apply-patches\n\n# a build.rs script is used to invoke the 'm4-firmware' project build\n# required because we can't have a normal dependency on a thing for a different target (A9/M4)\ncargo fel4 build\n```\n\n## Running\n\nOn UART1 (U-boot/A9) console:\n\n```text\nU-Boot 2017.07-28767-g87d490f (Jun 20 2018 - 10:29:54 -0700)\n\nCPU:   Freescale i.MX6SX rev1.3 at 792 MHz\nReset cause: POR\nBoard: nitrogen6sx\nI2C:   ready\nDRAM:  1 GiB\nMMC:   FSL_SDHC: 0, FSL_SDHC: 1\nSF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB\nDisplay: lcd:1280x720M@60 (1280x720)\nIn:    serial\nOut:   serial\nErr:   serial\nNet:   AR8035 at 4\nAR8035 at 5\nFEC0 [PRIME], FEC1, usb_ether\nHit any key to stop autoboot:  0\nUsing FEC0 device\nFilename 'feL4img'.\nLoad address: 0x83000000\nLoading: #################################################################\n         ############################\n         7.7 MiB/s\ndone\nBytes transferred = 1363524 (14ce44 hex)\n## Starting application at 0x83000000 ...\n\nELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10\n  paddr=[83000000..8315ffff]\nELF-loading image 'kernel'\n  paddr=[80000000..80032fff]\n  vaddr=[e0000000..e0032fff]\n  virt_entry=e0000000\nELF-loading image 'root-task'\n  paddr=[80033000..82080fff]\n  vaddr=[10000..205dfff]\n  virt_entry=10554\nEnabling MMU and paging\nJumping to kernel-image entry point...\n\nBootstrapping kernel\nBooting all finished, dropped to user space\nfeL4 app init\n\nhello from a feL4 thread!\n\nSRC paddr = 0x20D8000 -- vaddr = 0x10000000\nCCM paddr = 0x20C4000 -- vaddr = 0x10001000\nTCM paddr = 0x7F8000 -- vaddr = 0x10002000\n\ncreated new CPIO reader\nReader {\n    archive_size: 3584,\n    base_ptr: 0x00044010\n}\n\nparsed CPIO entry 'm4-firmware.bin'\n\nenabling M4 core clock\ncopying M4 binary to TCM - 3044 bytes\nenabling and starting the M4 core\nwaiting for SRC_SCR reset auto-clear (bit 3) to clear\n\nthread work all done, going to fault now\n\n!!! Fault from badge 0xBEEF\n```\n\nOn UART2 (M4) console:\n\n```text\nM4 core is up and running\n\nHello world from Rust on Cortex-M4\nHello world from Rust on Cortex-M4\nHello world from Rust on Cortex-M4\nHello world from Rust on Cortex-M4\nHello world from Rust on Cortex-M4\nHello world from Rust on Cortex-M4\n...\n```\n\n### A9 Test Deployment\n\n```bash\ntftp ${a9ocramloadaddr} ${serverip}:a9.bin\n\ngo ${a9ocramloadaddr}\n```\n\n### M4 Test Deployment\n\n```bash\ntftp ${m4loadaddr} ${serverip}:m4.bin\n\ndcache flush\n\nbootaux ${m4loadaddr}\n```\n\n## Notes\n\n### L2 Cache\n\nseL4 is attempting to use the TCM region for L2 cache.\nSince we're using it for the M4 core, can we instead use the\nregion at `0x009C_0000`; which is 256 KB, labeled as\n`L2 cache memory used as OCRAM aliased`?\n\nCould just be an issue with my config.\n\nL2 cache is configured as OCRAM by default I think.\nSee Table 8-2 in the TRM, fuse `USE_L2_CACHE_AS_OCRAM BOOT_CFG2`.\n\n### Memory Map\n\nThe i.MX6 SoloX has two cores with different address mapping.\n\nThe ARM IP Bus (AIPS) memory map shows there is a `0x4000_0000` offset\nfrom the A9's address space to the M4's.\n\nRefer to Table 2-1 (System memory map) for Cortex-A9 core and\nto Table 2-2 (CM4 memory map) for Cortex-M4 of the i.MX6 SoloX\nreference ranual.\n\nTo run Cortex-M4 it is needed to fill `TCM(L)`, that\nis addressed as `TCML ALIAS` (from zero).\n\nThe same memory is mapped to `0x007f8000` of the\nCortex-A9 (non-reflected in the Table 2-1).\n\nNote, this area is accessible by the Cortex-A9 after M4 clock\nis enabled in `CCM_CCGR3`.\n\n[solox]: https://boundarydevices.com/product/nit6_solox-imx6/\n[bd-article]: https://boundarydevices.com/using-the-cortex-m4-mcu-on-the-nit6_solox/\n[trm]: http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6SXRM.pdf\n[open-amp]: https://github.com/OpenAMP/open-amp/wiki\n","funding_links":[],"categories":[],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjonlamb-gh%2Fsolox-amp-rust","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjonlamb-gh%2Fsolox-amp-rust","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjonlamb-gh%2Fsolox-amp-rust/lists"}