{"id":20074130,"url":"https://github.com/juniper/open-register-design-tool","last_synced_at":"2026-01-27T17:35:59.503Z","repository":{"id":46536657,"uuid":"61146698","full_name":"Juniper/open-register-design-tool","owner":"Juniper","description":"Tool to generate register RTL, models, and docs using SystemRDL or JSpec input","archived":false,"fork":false,"pushed_at":"2024-10-21T20:31:57.000Z","size":7420,"stargazers_count":196,"open_issues_count":25,"forks_count":71,"subscribers_count":44,"default_branch":"master","last_synced_at":"2025-02-17T04:17:19.118Z","etag":null,"topics":["asic","eda","fpga","jspec","register-descriptions","registers","systemrdl","systemrdl-compiler","systemverilog","uvm"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Juniper.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2016-06-14T18:33:32.000Z","updated_at":"2025-01-21T02:48:49.000Z","dependencies_parsed_at":"2024-01-17T08:00:02.487Z","dependency_job_id":"b329713a-7dc9-4d6d-824f-a50d3f52d593","html_url":"https://github.com/Juniper/open-register-design-tool","commit_stats":null,"previous_names":[],"tags_count":19,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Juniper%2Fopen-register-design-tool","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Juniper%2Fopen-register-design-tool/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Juniper%2Fopen-register-design-tool/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Juniper%2Fopen-register-design-tool/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Juniper","download_url":"https://codeload.github.com/Juniper/open-register-design-tool/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":241505087,"owners_count":19973346,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","eda","fpga","jspec","register-descriptions","registers","systemrdl","systemrdl-compiler","systemverilog","uvm"],"created_at":"2024-11-13T14:49:31.567Z","updated_at":"2026-01-27T17:35:59.471Z","avatar_url":"https://github.com/Juniper.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# open-register-design-tool\n\nOrdt is a tool for automation of IC register definition and documentation.  It currently supports 2 input formats:\n  1. SystemRDL - a stardard register description format released by [Accellera.org](http://accellera.org/activities/working-groups/systemrdl)\n  2. JSpec - a register description format used within Juniper Networks\n\nThe tool can generate several outputs from SystemRDL or JSpec, including:\n  - SystemVerilog/Verilog RTL code description of registers\n  - UVM model of the registers\n  - C++ and python models of the registers\n  - C header file providing register address and field defines\n  - XML and text file register descriptions\n  - SystemRDL and JSpec (conversion)\n\nEasiest way to get started with ordt is to download a runnable jar from the [Juniper repo release area](https://github.com/Juniper/open-register-design-tool/releases).\nOrdt documentation can be found [here](https://github.com/Juniper/open-register-design-tool/wiki).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjuniper%2Fopen-register-design-tool","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fjuniper%2Fopen-register-design-tool","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fjuniper%2Fopen-register-design-tool/lists"}