{"id":25074968,"url":"https://github.com/karanraj06/riscv-32i-simulator","last_synced_at":"2025-04-15T00:13:37.017Z","repository":{"id":156856018,"uuid":"608241695","full_name":"Karanraj06/riscv-32i-simulator","owner":"Karanraj06","description":"RISCV-32I Simulator for executing machine code with single cycle and pipelined processor design","archived":false,"fork":false,"pushed_at":"2024-04-19T08:18:31.000Z","size":1054,"stargazers_count":6,"open_issues_count":1,"forks_count":3,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-04-15T00:13:12.159Z","etag":null,"topics":["fastapi","flask","react","risc-v"],"latest_commit_sha":null,"homepage":"https://riscv-32i-simulator-v2.netlify.app","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Karanraj06.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-03-01T16:00:50.000Z","updated_at":"2024-03-17T04:44:24.000Z","dependencies_parsed_at":"2025-02-07T00:31:39.211Z","dependency_job_id":null,"html_url":"https://github.com/Karanraj06/riscv-32i-simulator","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Karanraj06%2Friscv-32i-simulator","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Karanraj06%2Friscv-32i-simulator/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Karanraj06%2Friscv-32i-simulator/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Karanraj06%2Friscv-32i-simulator/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Karanraj06","download_url":"https://codeload.github.com/Karanraj06/riscv-32i-simulator/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":248981270,"owners_count":21193147,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fastapi","flask","react","risc-v"],"created_at":"2025-02-07T00:19:55.870Z","updated_at":"2025-04-15T00:13:37.001Z","avatar_url":"https://github.com/Karanraj06.png","language":"Python","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISCV-32I-Simulator\n\nFunctional Simulator for a subset of RISC-V Instruction Set. RISC-V is an open-source Instruction Set Architecture (ISA) that has gained popularity in recent years due to its simplicity and extensibility. The simulator reads encoded instructions from a memory file (machine code), decodes, executes, and writes back the results to a register file.\n\n## Overview\n\nThe project implements a functional simulator for a subset of RISC-V Instruction Set using a single-cycle processor design.\u003cbr\u003eThe simulator has two components:\n\n- Command Line Interface (CLI)\u003cbr\u003eThe CLI component is explained [here](single_cycle/README.md) detail\n\n- Graphical User Interface (GUI) built with Flask and Tailwind\u003cbr\u003eThe webapp is available at the following url: http://karanraj.pythonanywhere.com/\n\n## File Structure\n\n```\n.\n├── README.md\n├── docs\n│   └── reference.docx\n├── single_cycle\n│   ├── README.md\n│   ├── decode.py\n│   ├── execute.py\n│   ├── input.mc\n│   ├── instruction_fetch.py\n│   ├── main.py\n│   ├── memory_access.py\n│   ├── output.txt\n│   ├── registers.py\n│   └── write_back.py\n├── single_cycle_webapp\n│   │── README.md\n│   │── app.py\n│   │── ...\n│   └── write_back.py\n└── test\n    ├── array_sum.mc\n    ├── array_sum.s\n    ├── bubble_sort.mc\n    ├── bubble_sort.s\n    ├── fibonacci.mc\n    └── fibonacci.s\n```\n\nThe `single_cycle` folder contains the source code for the CLI component of the simulator. The `single_cycle_webapp` folder contains the source code for the GUI component of the simulator. The `test` folder contains some sample programs to test the simulator's correctness.\n\n## Supported Instructions\n\nThe simulator supports the following instructions:\n\n```\nR-Type: ADD, SUB, XOR, OR, AND, SLL, SRL, SRA\nI-Type: ADDI, XORI, ORI, ANDI, SLLI, SRLI, SRAI, LB, LH, LW, JALR\nS-Type: SB, SH, SW\nB-Type: BEQ, BNE, BGE, BLT\nU-Type: AUIPC, LUI\nJ-Type: JAL\n```\n\nEach instruction performs a specific operation such as arithmetic, logical, or control flow. For example, the ADDI instruction adds an immediate value to a register.\n\n## Group Members\n\n[@AtharvaMulay25](https://github.com/AtharvaMulay25)\u003cbr\u003e[@Karanraj06](https://github.com/Karanraj06)\u003cbr\u003e[@nishad-dhuri-05](https://github.com/nishad-dhuri-05)\u003cbr\u003e[@SumitPatil0404](https://github.com/SumitPatil0404)\n\n## Documentation\n\nPlease refer to the `reference.docx` file in the `docs` folder for more information on how to use the simulator","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fkaranraj06%2Friscv-32i-simulator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fkaranraj06%2Friscv-32i-simulator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fkaranraj06%2Friscv-32i-simulator/lists"}