{"id":13461341,"url":"https://github.com/klauspost/cpuid","last_synced_at":"2025-05-16T01:02:52.672Z","repository":{"id":30329114,"uuid":"33881440","full_name":"klauspost/cpuid","owner":"klauspost","description":"CPU feature identification for Go","archived":false,"fork":false,"pushed_at":"2025-03-19T21:57:52.000Z","size":2556,"stargazers_count":1090,"open_issues_count":4,"forks_count":136,"subscribers_count":27,"default_branch":"master","last_synced_at":"2025-05-09T00:53:59.684Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Go","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/klauspost.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":"CONTRIBUTING.txt","funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2015-04-13T16:57:56.000Z","updated_at":"2025-05-08T12:32:34.000Z","dependencies_parsed_at":"2024-11-05T23:03:42.524Z","dependency_job_id":"2b77ba8a-d66c-4e42-9372-cec1250cbab3","html_url":"https://github.com/klauspost/cpuid","commit_stats":{"total_commits":173,"total_committers":28,"mean_commits":6.178571428571429,"dds":"0.23699421965317924","last_synced_commit":"ee7cba987ff4d8747807f9e616ac1b8fac8119b9"},"previous_names":[],"tags_count":39,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/klauspost%2Fcpuid","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/klauspost%2Fcpuid/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/klauspost%2Fcpuid/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/klauspost%2Fcpuid/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/klauspost","download_url":"https://codeload.github.com/klauspost/cpuid/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254042572,"owners_count":22004905,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-07-31T11:00:35.124Z","updated_at":"2025-05-16T01:02:52.632Z","avatar_url":"https://github.com/klauspost.png","language":"Go","funding_links":[],"categories":["Go","开源类库","Open source library","Hardware"],"sub_categories":["系统信息","System Message"],"readme":"# cpuid\nPackage cpuid provides information about the CPU running the current program.\n\nCPU features are detected on startup, and kept for fast access through the life of the application.\nCurrently x86 / x64 (AMD64/i386) and ARM (ARM64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.\n\nYou can access the CPU information by accessing the shared CPU variable of the cpuid library.\n\nPackage home: https://github.com/klauspost/cpuid\n\n[![PkgGoDev](https://pkg.go.dev/badge/github.com/klauspost/cpuid)](https://pkg.go.dev/github.com/klauspost/cpuid/v2)\n[![Go](https://github.com/klauspost/cpuid/actions/workflows/go.yml/badge.svg)](https://github.com/klauspost/cpuid/actions/workflows/go.yml)\n\n## installing\n\n`go get -u github.com/klauspost/cpuid/v2` using modules.\nDrop `v2` for others.\n\nInstalling binary:\n\n`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`\n\nOr download binaries from release page: https://github.com/klauspost/cpuid/releases\n\n### Homebrew\n\nFor macOS/Linux users, you can install via [brew](https://brew.sh/)\n\n```sh\n$ brew install cpuid\n```\n\n## example\n\n```Go\npackage main\n\nimport (\n\t\"fmt\"\n\t\"strings\"\n\n\t. \"github.com/klauspost/cpuid/v2\"\n)\n\nfunc main() {\n\t// Print basic CPU information:\n\tfmt.Println(\"Name:\", CPU.BrandName)\n\tfmt.Println(\"PhysicalCores:\", CPU.PhysicalCores)\n\tfmt.Println(\"ThreadsPerCore:\", CPU.ThreadsPerCore)\n\tfmt.Println(\"LogicalCores:\", CPU.LogicalCores)\n\tfmt.Println(\"Family\", CPU.Family, \"Model:\", CPU.Model, \"Vendor ID:\", CPU.VendorID)\n\tfmt.Println(\"Features:\", strings.Join(CPU.FeatureSet(), \",\"))\n\tfmt.Println(\"Cacheline bytes:\", CPU.CacheLine)\n\tfmt.Println(\"L1 Data Cache:\", CPU.Cache.L1D, \"bytes\")\n\tfmt.Println(\"L1 Instruction Cache:\", CPU.Cache.L1I, \"bytes\")\n\tfmt.Println(\"L2 Cache:\", CPU.Cache.L2, \"bytes\")\n\tfmt.Println(\"L3 Cache:\", CPU.Cache.L3, \"bytes\")\n\tfmt.Println(\"Frequency\", CPU.Hz, \"hz\")\n\n\t// Test if we have these specific features:\n\tif CPU.Supports(SSE, SSE2) {\n\t\tfmt.Println(\"We have Streaming SIMD 2 Extensions\")\n\t}\n}\n```\n\nSample output:\n```\n\u003ego run main.go\nName: AMD Ryzen 9 3950X 16-Core Processor\nPhysicalCores: 16\nThreadsPerCore: 2\nLogicalCores: 32\nFamily 23 Model: 113 Vendor ID: AMD\nFeatures: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CMOV,CX16,F16C,FMA3,HTT,HYPERVISOR,LZCNT,MMX,MMXEXT,NX,POPCNT,RDRAND,RDSEED,RDTSCP,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3\nCacheline bytes: 64\nL1 Data Cache: 32768 bytes\nL1 Instruction Cache: 32768 bytes\nL2 Cache: 524288 bytes\nL3 Cache: 16777216 bytes\nFrequency 0 hz\nWe have Streaming SIMD 2 Extensions\n```\n\n# usage\n\nThe `cpuid.CPU` provides access to CPU features. Use `cpuid.CPU.Supports()` to check for CPU features.\nA faster `cpuid.CPU.Has()` is provided which will usually be inlined by the gc compiler. \n\nTo test a larger number of features, they can be combined using `f := CombineFeatures(CMOV, CMPXCHG8, X87, FXSR, MMX, SYSCALL, SSE, SSE2)`, etc.\nThis can be using with `cpuid.CPU.HasAll(f)` to quickly test if all features are supported.\n\nNote that for some cpu/os combinations some features will not be detected.\n`amd64` has rather good support and should work reliably on all platforms.\n\nNote that hypervisors may not pass through all CPU features through to the guest OS,\nso even if your host supports a feature it may not be visible on guests.\n\n## arm64 feature detection\n\nNot all operating systems provide ARM features directly \nand there is no safe way to do so for the rest.\n\nCurrently `arm64/linux` and `arm64/freebsd` should be quite reliable. \n`arm64/darwin` adds features expected from the M1 processor, but a lot remains undetected.\n\nA `DetectARM()` can be used if you are able to control your deployment,\nit will detect CPU features, but may crash if the OS doesn't intercept the calls.\nA `-cpu.arm` flag for detecting unsafe ARM features can be added. See below.\n \nNote that currently only features are detected on ARM, \nno additional information is currently available. \n\n## flags\n\nIt is possible to add flags that affects cpu detection.\n\nFor this the `Flags()` command is provided.\n\nThis must be called *before* `flag.Parse()` AND after the flags have been parsed `Detect()` must be called.\n\nThis means that any detection used in `init()` functions will not contain these flags.\n\nExample:\n\n```Go\npackage main\n\nimport (\n\t\"flag\"\n\t\"fmt\"\n\t\"strings\"\n\n\t\"github.com/klauspost/cpuid/v2\"\n)\n\nfunc main() {\n\tcpuid.Flags()\n\tflag.Parse()\n\tcpuid.Detect()\n\n\t// Test if we have these specific features:\n\tif cpuid.CPU.Supports(cpuid.SSE, cpuid.SSE2) {\n\t\tfmt.Println(\"We have Streaming SIMD 2 Extensions\")\n\t}\n}\n```\n\n## commandline\n\nDownload as binary from: https://github.com/klauspost/cpuid/releases\n\nInstall from source:\n\n`go install github.com/klauspost/cpuid/v2/cmd/cpuid@latest`\n\n### Example\n\n```\nλ cpuid\nName: AMD Ryzen 9 3950X 16-Core Processor\nVendor String: AuthenticAMD\nVendor ID: AMD\nPhysicalCores: 16\nThreads Per Core: 2\nLogical Cores: 32\nCPU Family 23 Model: 113\nFeatures: ADX,AESNI,AVX,AVX2,BMI1,BMI2,CLMUL,CLZERO,CMOV,CMPXCHG8,CPBOOST,CX16,F16C,FMA3,FXSR,FXSROPT,HTT,HYPERVISOR,LAHF,LZCNT,MCAOVERFLOW,MMX,MMXEXT,MOVBE,NX,OSXSAVE,POPCNT,RDRAND,RDSEED,RDTSCP,SCE,SHA,SSE,SSE2,SSE3,SSE4,SSE42,SSE4A,SSSE3,SUCCOR,X87,XSAVE\nMicroarchitecture level: 3\nCacheline bytes: 64\nL1 Instruction Cache: 32768 bytes\nL1 Data Cache: 32768 bytes\nL2 Cache: 524288 bytes\nL3 Cache: 16777216 bytes\n\n```\n### JSON Output:\n\n```\nλ cpuid --json\n{\n \"BrandName\": \"AMD Ryzen 9 3950X 16-Core Processor\",\n \"VendorID\": 2,\n \"VendorString\": \"AuthenticAMD\",\n \"PhysicalCores\": 16,\n \"ThreadsPerCore\": 2,\n \"LogicalCores\": 32,\n \"Family\": 23,\n \"Model\": 113,\n \"CacheLine\": 64,\n \"Hz\": 0,\n \"BoostFreq\": 0,\n \"Cache\": {\n \"L1I\": 32768,\n \"L1D\": 32768,\n \"L2\": 524288,\n \"L3\": 16777216\n },\n \"SGX\": {\n \"Available\": false,\n \"LaunchControl\": false,\n \"SGX1Supported\": false,\n \"SGX2Supported\": false,\n \"MaxEnclaveSizeNot64\": 0,\n \"MaxEnclaveSize64\": 0,\n \"EPCSections\": null\n },\n \"Features\": [\n \"ADX\",\n \"AESNI\",\n \"AVX\",\n \"AVX2\",\n \"BMI1\",\n \"BMI2\",\n \"CLMUL\",\n \"CLZERO\",\n \"CMOV\",\n \"CMPXCHG8\",\n \"CPBOOST\",\n \"CX16\",\n \"F16C\",\n \"FMA3\",\n \"FXSR\",\n \"FXSROPT\",\n \"HTT\",\n \"HYPERVISOR\",\n \"LAHF\",\n \"LZCNT\",\n \"MCAOVERFLOW\",\n \"MMX\",\n \"MMXEXT\",\n \"MOVBE\",\n \"NX\",\n \"OSXSAVE\",\n \"POPCNT\",\n \"RDRAND\",\n \"RDSEED\",\n \"RDTSCP\",\n \"SCE\",\n \"SHA\",\n \"SSE\",\n \"SSE2\",\n \"SSE3\",\n \"SSE4\",\n \"SSE42\",\n \"SSE4A\",\n \"SSSE3\",\n \"SUCCOR\",\n \"X87\",\n \"XSAVE\"\n ],\n \"X64Level\": 3\n}\n```\n\n### Check CPU microarch level\n\n```\nλ cpuid --check-level=3\n2022/03/18 17:04:40 AMD Ryzen 9 3950X 16-Core Processor\n2022/03/18 17:04:40 Microarchitecture level 3 is supported. Max level is 3.\nExit Code 0\n\nλ cpuid --check-level=4\n2022/03/18 17:06:18 AMD Ryzen 9 3950X 16-Core Processor\n2022/03/18 17:06:18 Microarchitecture level 4 not supported. Max level is 3.\nExit Code 1\n```\n\n\n## Available flags\n\n### x86 \u0026 amd64 \n\n| Feature Flag | Description |\n|--------------------|------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|\n| ADX | Intel ADX (Multi-Precision Add-Carry Instruction Extensions) |\n| AESNI | Advanced Encryption Standard New Instructions |\n| AMD3DNOW | AMD 3DNOW |\n| AMD3DNOWEXT | AMD 3DNowExt |\n| AMXBF16 | Tile computational operations on BFLOAT16 numbers |\n| AMXINT8 | Tile computational operations on 8-bit integers |\n| AMXFP16 | Tile computational operations on FP16 numbers |\n| AMXFP8 | Tile computational operations on FP8 numbers |\n| AMXCOMPLEX | Tile computational operations on complex numbers |\n| AMXTILE | Tile architecture |\n| AMXTF32 | Matrix Multiplication of TF32 Tiles into Packed Single Precision Tile |\n| AMXTRANSPOSE | Tile multiply where the first operand is transposed |\n| APX_F | Intel APX |\n| AVX | AVX functions |\n| AVX10 | If set the Intel AVX10 Converged Vector ISA is supported |\n| AVX10_128 | If set indicates that AVX10 128-bit vector support is present |\n| AVX10_256 | If set indicates that AVX10 256-bit vector support is present |\n| AVX10_512 | If set indicates that AVX10 512-bit vector support is present |\n| AVX2 | AVX2 functions |\n| AVX512BF16 | AVX-512 BFLOAT16 Instructions |\n| AVX512BITALG | AVX-512 Bit Algorithms |\n| AVX512BW | AVX-512 Byte and Word Instructions |\n| AVX512CD | AVX-512 Conflict Detection Instructions |\n| AVX512DQ | AVX-512 Doubleword and Quadword Instructions |\n| AVX512ER | AVX-512 Exponential and Reciprocal Instructions |\n| AVX512F | AVX-512 Foundation |\n| AVX512FP16 | AVX-512 FP16 Instructions |\n| AVX512IFMA | AVX-512 Integer Fused Multiply-Add Instructions |\n| AVX512PF | AVX-512 Prefetch Instructions |\n| AVX512VBMI | AVX-512 Vector Bit Manipulation Instructions |\n| AVX512VBMI2 | AVX-512 Vector Bit Manipulation Instructions, Version 2 |\n| AVX512VL | AVX-512 Vector Length Extensions |\n| AVX512VNNI | AVX-512 Vector Neural Network Instructions |\n| AVX512VP2INTERSECT | AVX-512 Intersect for D/Q |\n| AVX512VPOPCNTDQ | AVX-512 Vector Population Count Doubleword and Quadword |\n| AVXIFMA | AVX-IFMA instructions |\n| AVXNECONVERT | AVX-NE-CONVERT instructions |\n| AVXSLOW | Indicates the CPU performs 2 128 bit operations instead of one |\n| AVXVNNI | AVX (VEX encoded) VNNI neural network instructions |\n| AVXVNNIINT8 | AVX-VNNI-INT8 instructions |\n| AVXVNNIINT16 | AVX-VNNI-INT16 instructions |\n| BHI_CTRL | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 |\n| BMI1 | Bit Manipulation Instruction Set 1 |\n| BMI2 | Bit Manipulation Instruction Set 2 |\n| CETIBT | Intel CET Indirect Branch Tracking |\n| CETSS | Intel CET Shadow Stack |\n| CLDEMOTE | Cache Line Demote |\n| CLMUL | Carry-less Multiplication |\n| CLZERO | CLZERO instruction supported |\n| CMOV | i686 CMOV |\n| CMPCCXADD | CMPCCXADD instructions |\n| CMPSB_SCADBS_SHORT | Fast short CMPSB and SCASB |\n| CMPXCHG8 | CMPXCHG8 instruction |\n| CPBOOST | Core Performance Boost |\n| CPPC | AMD: Collaborative Processor Performance Control |\n| CX16 | CMPXCHG16B Instruction |\n| EFER_LMSLE_UNS | AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ |\n| ENQCMD | Enqueue Command |\n| ERMS | Enhanced REP MOVSB/STOSB |\n| F16C | Half-precision floating-point conversion |\n| FLUSH_L1D | Flush L1D cache |\n| FMA3 | Intel FMA 3. Does not imply AVX. |\n| FMA4 | Bulldozer FMA4 functions |\n| FP128 | AMD: When set, the internal FP/SIMD execution datapath is 128-bits wide |\n| FP256 | AMD: When set, the internal FP/SIMD execution datapath is 256-bits wide |\n| FSRM | Fast Short Rep Mov |\n| FXSR | FXSAVE, FXRESTOR instructions, CR4 bit 9 |\n| FXSROPT | FXSAVE/FXRSTOR optimizations |\n| GFNI | Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage. |\n| HLE | Hardware Lock Elision |\n| HRESET | If set CPU supports history reset and the IA32_HRESET_ENABLE MSR |\n| HTT | Hyperthreading (enabled) |\n| HWA | Hardware assert supported. Indicates support for MSRC001_10 |\n| HYBRID_CPU | This part has CPUs of more than one type. |\n| HYPERVISOR | This bit has been reserved by Intel \u0026 AMD for use by hypervisors |\n| IA32_ARCH_CAP | IA32_ARCH_CAPABILITIES MSR (Intel) |\n| IA32_CORE_CAP | IA32_CORE_CAPABILITIES MSR |\n| IBPB | Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB) |\n| IBRS | AMD: Indirect Branch Restricted Speculation |\n| IBRS_PREFERRED | AMD: IBRS is preferred over software solution |\n| IBRS_PROVIDES_SMP | AMD: IBRS provides Same Mode Protection |\n| IBS | Instruction Based Sampling (AMD) |\n| IBSBRNTRGT | Instruction Based Sampling Feature (AMD) |\n| IBSFETCHSAM | Instruction Based Sampling Feature (AMD) |\n| IBSFFV | Instruction Based Sampling Feature (AMD) |\n| IBSOPCNT | Instruction Based Sampling Feature (AMD) |\n| IBSOPCNTEXT | Instruction Based Sampling Feature (AMD) |\n| IBSOPSAM | Instruction Based Sampling Feature (AMD) |\n| IBSRDWROPCNT | Instruction Based Sampling Feature (AMD) |\n| IBSRIPINVALIDCHK | Instruction Based Sampling Feature (AMD) |\n| IBS_FETCH_CTLX | AMD: IBS fetch control extended MSR supported |\n| IBS_OPDATA4 | AMD: IBS op data 4 MSR supported |\n| IBS_OPFUSE | AMD: Indicates support for IbsOpFuse |\n| IBS_PREVENTHOST | Disallowing IBS use by the host supported |\n| IBS_ZEN4 | Fetch and Op IBS support IBS extensions added with Zen4 |\n| IDPRED_CTRL | IPRED_DIS |\n| INT_WBINVD | WBINVD/WBNOINVD are interruptible. |\n| INVLPGB | NVLPGB and TLBSYNC instruction supported |\n| KEYLOCKER | Key locker |\n| KEYLOCKERW | Key locker wide |\n| LAHF | LAHF/SAHF in long mode |\n| LAM | If set, CPU supports Linear Address Masking |\n| LBRVIRT | LBR virtualization |\n| LZCNT | LZCNT instruction |\n| MCAOVERFLOW | MCA overflow recovery support. |\n| MCDT_NO | Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it. |\n| MCOMMIT | MCOMMIT instruction supported |\n| MD_CLEAR | VERW clears CPU buffers |\n| MMX | standard MMX |\n| MMXEXT | SSE integer functions or AMD MMX ext |\n| MOVBE | MOVBE instruction (big-endian) |\n| MOVDIR64B | Move 64 Bytes as Direct Store |\n| MOVDIRI | Move Doubleword as Direct Store |\n| MOVSB_ZL | Fast Zero-Length MOVSB |\n| MPX | Intel MPX (Memory Protection Extensions) |\n| MOVU | MOVU SSE instructions are more efficient and should be preferred to SSE\tMOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD |\n| MSRIRC | Instruction Retired Counter MSR available |\n| MSRLIST | Read/Write List of Model Specific Registers |\n| MSR_PAGEFLUSH | Page Flush MSR available |\n| NRIPS | Indicates support for NRIP save on VMEXIT |\n| NX | NX (No-Execute) bit |\n| OSXSAVE | XSAVE enabled by OS |\n| PCONFIG | PCONFIG for Intel Multi-Key Total Memory Encryption |\n| POPCNT | POPCNT instruction |\n| PPIN | AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled |\n| PREFETCHI | PREFETCHIT0/1 instructions |\n| PSFD | Predictive Store Forward Disable |\n| RDPRU | RDPRU instruction supported |\n| RDRAND | RDRAND instruction is available |\n| RDSEED | RDSEED instruction is available |\n| RDTSCP | RDTSCP Instruction |\n| RRSBA_CTRL | Restricted RSB Alternate |\n| RTM | Restricted Transactional Memory |\n| RTM_ALWAYS_ABORT | Indicates that the loaded microcode is forcing RTM abort. |\n| SERIALIZE | Serialize Instruction Execution |\n| SEV | AMD Secure Encrypted Virtualization supported |\n| SEV_64BIT | AMD SEV guest execution only allowed from a 64-bit host |\n| SEV_ALTERNATIVE | AMD SEV Alternate Injection supported |\n| SEV_DEBUGSWAP | Full debug state swap supported for SEV-ES guests |\n| SEV_ES | AMD SEV Encrypted State supported |\n| SEV_RESTRICTED | AMD SEV Restricted Injection supported |\n| SEV_SNP | AMD SEV Secure Nested Paging supported |\n| SGX | Software Guard Extensions |\n| SGXLC | Software Guard Extensions Launch Control |\n| SHA | Intel SHA Extensions |\n| SME | AMD Secure Memory Encryption supported |\n| SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced |\n| SM3_X86 | SM3 instructions |\n| SM4_X86 | SM4 instructions |\n| SPEC_CTRL_SSBD | Speculative Store Bypass Disable |\n| SRBDS_CTRL | SRBDS mitigation MSR available |\n| SSE | SSE functions |\n| SSE2 | P4 SSE functions |\n| SSE3 | Prescott SSE3 functions |\n| SSE4 | Penryn SSE4.1 functions |\n| SSE42 | Nehalem SSE4.2 functions |\n| SSE4A | AMD Barcelona microarchitecture SSE4a instructions |\n| SSSE3 | Conroe SSSE3 functions |\n| STIBP | Single Thread Indirect Branch Predictors |\n| STIBP_ALWAYSON | AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On |\n| STOSB_SHORT | Fast short STOSB |\n| SUCCOR | Software uncorrectable error containment and recovery capability. |\n| SVM | AMD Secure Virtual Machine |\n| SVMDA | Indicates support for the SVM decode assists. |\n| SVMFBASID | SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control |\n| SVML | AMD SVM lock. Indicates support for SVM-Lock. |\n| SVMNP | AMD SVM nested paging |\n| SVMPF | SVM pause intercept filter. Indicates support for the pause intercept filter |\n| SVMPFT | SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold |\n| SYSCALL | System-Call Extension (SCE): SYSCALL and SYSRET instructions. |\n| SYSEE | SYSENTER and SYSEXIT instructions |\n| TBM | AMD Trailing Bit Manipulation |\n| TDX_GUEST | Intel Trust Domain Extensions Guest |\n| TLB_FLUSH_NESTED | AMD: Flushing includes all the nested translations for guest translations |\n| TME | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE. |\n| TOPEXT | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX. |\n| TSCRATEMSR | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104 |\n| TSXLDTRK | Intel TSX Suspend Load Address Tracking |\n| VAES | Vector AES. AVX(512) versions requires additional checks. |\n| VMCBCLEAN | VMCB clean bits. Indicates support for VMCB clean bits. |\n| VMPL | AMD VM Permission Levels supported |\n| VMSA_REGPROT | AMD VMSA Register Protection supported |\n| VMX | Virtual Machine Extensions |\n| VPCLMULQDQ | Carry-Less Multiplication Quadword. Requires AVX for 3 register versions. |\n| VTE | AMD Virtual Transparent Encryption supported |\n| WAITPKG | TPAUSE, UMONITOR, UMWAIT |\n| WBNOINVD | Write Back and Do Not Invalidate Cache |\n| WRMSRNS | Non-Serializing Write to Model Specific Register |\n| X87 | FPU |\n| XGETBV1 | Supports XGETBV with ECX = 1 |\n| XOP | Bulldozer XOP functions |\n| XSAVE | XSAVE, XRESTOR, XSETBV, XGETBV |\n| XSAVEC | Supports XSAVEC and the compacted form of XRSTOR. |\n| XSAVEOPT | XSAVEOPT available |\n| XSAVES | Supports XSAVES/XRSTORS and IA32_XSS |\n\n# ARM features:\n\n| Feature Flag | Description |\n|--------------|------------------------------------------------------------------|\n| AESARM | AES instructions |\n| ARMCPUID | Some CPU ID registers readable at user-level |\n| ASIMD | Advanced SIMD |\n| ASIMDDP | SIMD Dot Product |\n| ASIMDHP | Advanced SIMD half-precision floating point |\n| ASIMDRDM | Rounding Double Multiply Accumulate/Subtract (SQRDMLAH/SQRDMLSH) |\n| ATOMICS | Large System Extensions (LSE) |\n| CRC32 | CRC32/CRC32C instructions |\n| DCPOP | Data cache clean to Point of Persistence (DC CVAP) |\n| EVTSTRM | Generic timer |\n| FCMA | Floatin point complex number addition and multiplication |\n| FHM | FMLAL and FMLSL instructions |\n| FP | Single-precision and double-precision floating point |\n| FPHP | Half-precision floating point |\n| GPA | Generic Pointer Authentication |\n| JSCVT | Javascript-style double-\u003eint convert (FJCVTZS) |\n| LRCPC | Weaker release consistency (LDAPR, etc) |\n| PMULL | Polynomial Multiply instructions (PMULL/PMULL2) |\n| RNDR | Random Number instructions |\n| TLB | Outer Shareable and TLB range maintenance instructions |\n| TS | Flag manipulation instructions |\n| SHA1 | SHA-1 instructions (SHA1C, etc) |\n| SHA2 | SHA-2 instructions (SHA256H, etc) |\n| SHA3 | SHA-3 instructions (EOR3, RAXI, XAR, BCAX) |\n| SHA512 | SHA512 instructions |\n| SM3 | SM3 instructions |\n| SM4 | SM4 instructions |\n| SVE | Scalable Vector Extension |\n\n# license\n\nThis code is published under an MIT license. See LICENSE file for more information.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fklauspost%2Fcpuid","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fklauspost%2Fcpuid","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fklauspost%2Fcpuid/lists"}