{"id":50873827,"url":"https://github.com/ksenginew/nanoprocessor","last_synced_at":"2026-06-15T07:35:02.249Z","repository":{"id":358727518,"uuid":"1222744173","full_name":"ksenginew/nanoprocessor","owner":"ksenginew","description":"A small 4-bit nanoprocessor designed in VHDL for Xilinx Vivado. The project includes a register bank, ALU, program counter, ROM-based instruction memory, a clock divider, and a seven-segment output path for displaying register data on BASYS 3.","archived":false,"fork":false,"pushed_at":"2026-05-18T19:56:31.000Z","size":1743,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2026-05-18T21:59:03.867Z","etag":null,"topics":["hardware","hardware-designs","microprocessor","processor","vhdl","vivado"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ksenginew.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null},"funding":{"github":null,"open_collective":"ksengine","custom":["buymeacoff.ee/ksengine"]}},"created_at":"2026-04-27T17:02:36.000Z","updated_at":"2026-05-18T19:56:35.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/ksenginew/nanoprocessor","commit_stats":null,"previous_names":["ksenginew/nanoprocessor"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/ksenginew/nanoprocessor","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ksenginew%2Fnanoprocessor","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ksenginew%2Fnanoprocessor/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ksenginew%2Fnanoprocessor/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ksenginew%2Fnanoprocessor/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ksenginew","download_url":"https://codeload.github.com/ksenginew/nanoprocessor/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ksenginew%2Fnanoprocessor/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":34353193,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-06-15T02:00:07.085Z","response_time":63,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["hardware","hardware-designs","microprocessor","processor","vhdl","vivado"],"created_at":"2026-06-15T07:35:01.367Z","updated_at":"2026-06-15T07:35:02.243Z","avatar_url":"https://github.com/ksenginew.png","language":"VHDL","funding_links":["https://opencollective.com/ksengine","buymeacoff.ee/ksengine"],"categories":[],"sub_categories":[],"readme":"# Nanoprocessor\n\nA small 4-bit nanoprocessor designed in VHDL for Xilinx Vivado. The project includes a register bank, ALU, program counter, ROM-based instruction memory, a clock divider, and a seven-segment output path for displaying register data on BASYS 3.\n\nThe repository also contains a custom Python assembler that translates a readable assembly language into 12-bit machine code and can emit a VHDL ROM initialization file for simulation or synthesis.\n\n## What This Project Includes\n\n- A complete top-level processor in VHDL.\n- Reusable logic blocks such as adders, multiplexers, decoders, registers, ROM, and a register file.\n- A simulation testbench set for individual modules and the top-level CPU.\n- A custom assembler with support for labels, pseudo-instructions, and multiple immediate formats.\n- A report and ISA reference documenting the design choices and instruction encoding.\n\n## Repository Layout\n\n- `nanoprocessor.srcs/sources_1/new/` - synthesizable VHDL source files.\n- `nanoprocessor.srcs/sim_1/new/` - VHDL testbenches for modules and the top-level CPU.\n- `assembler/` - Python assembler and sample assembly program.\n- `isa.md` - instruction set reference.\n- `report.md` - lab report and design write-up.\n\n## Top-Level Architecture\n\nThe main entity is `Nanoprocessor` in `nanoprocessor.srcs/sources_1/new/Nanoprocessor.vhd`. It connects the following major blocks:\n\n- Program Counter\n- Instruction Decoder\n- ROM\n- Register Bank\n- 4-bit Add/Sub unit\n- 2-way and 8-way multiplexers\n- Clock Divider\n- 7-segment lookup table\n\nThe processor uses 12-bit instructions and 3-bit register addresses, giving access to eight registers, with `R0` hardwired to zero.\n\n## Instruction Set\n\nThe hardware implements four base instructions:\n\n- `ADD A, B, C`\n- `SUB A, B, C`\n- `ADDI A, B, I`\n- `BEQ A, I, D`\n\nSee `isa.md` for the full ISA reference, including pseudo-instructions such as:\n\n- `MOV`, `MV`\n- `MOVI`, `MVI`\n- `CLR`\n- `NEG`\n- `INC`, `DEC`\n- `SUBI`\n- `MUL2`\n- `B`, `J`, `JMP`\n- `BEQZ`, `JZR`\n- `NOP`\n\n## Assembler\n\nThe assembler is in `assembler/main.py`. It performs a two-pass translation:\n\n1. Resolve labels.\n2. Translate pseudo-instructions into base instructions.\n3. Encode the result as 12-bit machine words.\n4. Write `.hex`, `.oct`, `.bin`, and `.vhdl` output files.\n\n### Run the sample program\n\n```powershell\npy .\\assembler\\main.py .\\assembler\\test.asm\n```\n\nThis will generate:\n\n- `assembler/test.hex`\n- `assembler/test.oct`\n- `assembler/test.bin`\n- `assembler/test.vhdl`\n\n### Supported immediates\n\nThe assembler accepts decimal, binary, octal, hexadecimal, negative values, and labels where the instruction format allows them.\n\n### Example program\n\n`assembler/test.asm` contains a short loop that computes the sum of `1 + 2 + 3` and leaves the result in `R7`.\n\n## Simulation\n\nEach main source block has a matching testbench in `nanoprocessor.srcs/sim_1/new/`. Useful benches include:\n\n- `tb_Nanoprocessor.vhd`\n- `tb_Clock_Divider.vhd`\n- `TB_Reg_Bank.vhd`\n- `tb_Instruction_Decoder.vhd`\n- `TB_MUX_2_way_3_bit.vhd`\n- `TB_MUX_2_way_4_bit.vhd`\n- `TB_MUX_8_way_4_bit.vhd`\n- `TB_Decoder_2_to_4.vhd`\n- `TB_Decoder_3_to_8.vhd`\n- `D_FF_tb.vhd`\n- `TB_FA.vhd`\n- `TB_LUT_16_7.vhd`\n- `TB_Rom.vhd`\n\nThe top-level testbench uses a shortened clock-divider preload so simulation runs quickly.\n\n## Vivado Workflow\n\n1. Open `nanoprocessor.xpr` in Vivado.\n2. Run synthesis.\n3. Run simulation on the desired testbench.\n4. Run implementation.\n5. Generate the bitstream if you want to program the BASYS 3 board.\n\n## Notes on Hardware Deployment\n\n- The design uses a clock divider so the processor can be observed at a human-friendly speed on hardware.\n- Output is routed to LEDs and a seven-segment display.\n- The project was built around BASYS 3 constraints, with board pin mapping handled through `nanoprocessor.srcs/constrs_1/new/Basys3.xdc`.\n\n## Design Style\n\nSeveral modules are implemented in a gate-level or structural style rather than with high-level behavioral VHDL. This keeps the datapath explicit and makes the design easier to study for computer organization and digital design labs.\n\n## Getting Started\n\nIf you just want to inspect the project, start with these files:\n\n- `README.md`\n- `isa.md`\n- `nanoprocessor.srcs/sources_1/new/Nanoprocessor.vhd`\n- `assembler/main.py`\n- `assembler/test.asm`\n\nIf you want to verify behavior, begin with `tb_Nanoprocessor.vhd` and the module testbenches in `nanoprocessor.srcs/sim_1/new/`.\n\n## Team Credits\n\nThis project was completed by a 4-member team. Core responsibilities were split as follows:\n\n- K.A.K.K. Santhusa - Instruction Decoder, Program ROM, and custom Python assembler.\n- W. A. A. T. Silva - Multiplexers and decoders, including manual basic-gate Boolean optimization.\n- G.Y.S Sanjaya - Arithmetic units, including the adders/subtractors, and the Program Counter.\n- P.D.Y Sewwandi - Register file design, project documentation, and report writing.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fksenginew%2Fnanoprocessor","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fksenginew%2Fnanoprocessor","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fksenginew%2Fnanoprocessor/lists"}