{"id":20993348,"url":"https://github.com/kushrm2803/risc-v_assembler","last_synced_at":"2025-10-13T12:44:21.953Z","repository":{"id":226282739,"uuid":"767939720","full_name":"kushrm2803/RISC-V_Assembler","owner":"kushrm2803","description":"Simple RISC-V assembler program based on Venus that converts RISC-V assembly language (.asm) into machine language (.mc) format.","archived":false,"fork":false,"pushed_at":"2024-03-26T20:03:30.000Z","size":3197,"stargazers_count":2,"open_issues_count":0,"forks_count":2,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-07-09T21:17:19.343Z","etag":null,"topics":["assembly","branch-prediction","risc-v","venus"],"latest_commit_sha":null,"homepage":"","language":"Assembly","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/kushrm2803.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2024-03-06T07:10:33.000Z","updated_at":"2025-06-18T19:57:16.000Z","dependencies_parsed_at":"2025-07-09T19:58:22.438Z","dependency_job_id":"6ba99206-39f8-4012-a867-583e7188008d","html_url":"https://github.com/kushrm2803/RISC-V_Assembler","commit_stats":null,"previous_names":["kushrm2803/risc-v_assembler"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/kushrm2803/RISC-V_Assembler","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/kushrm2803%2FRISC-V_Assembler","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/kushrm2803%2FRISC-V_Assembler/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/kushrm2803%2FRISC-V_Assembler/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/kushrm2803%2FRISC-V_Assembler/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/kushrm2803","download_url":"https://codeload.github.com/kushrm2803/RISC-V_Assembler/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/kushrm2803%2FRISC-V_Assembler/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":279015057,"owners_count":26085643,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-10-13T02:00:06.723Z","response_time":61,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembly","branch-prediction","risc-v","venus"],"created_at":"2024-11-19T07:14:37.029Z","updated_at":"2025-10-13T12:44:21.917Z","avatar_url":"https://github.com/kushrm2803.png","language":"Assembly","funding_links":[],"categories":[],"sub_categories":[],"readme":"# RISC-V Assembler\n\nThis is a simple RISC-V assembler program based on Venus that converts RISC-V assembly language (.asm) into machine language (.mc) format. The program supports both .text and .data sections.(The support for pseudo instructions and floating-point operations is not included).Additionally, it includes a basic branch predictor implementation to evaluate the accuracy of various branch prediction methods.\n\n## Supported Instructions\n\nThe program supports the following RISC-V 32-bit ISA instructions:\n\n### R Format\n- `add`, `and`, `or`, `sll`, `slt`, `sra`, `srl`, `sub`, `xor`, `mul`, `div`, `rem`\n\n### I Format\n- `addi`, `andi`, `ori`, `lb`, `ld`, `lh`, `lw`, `jalr`\n\n### S Format\n- `sb`, `sw`, `sd`, `sh`\n\n### SB Format\n- `beq`, `bne`, `bge`, `blt`\n\n### U Format\n- `auipc`, `lui`\n\n### UJ Format\n- `jal`\n\n## Assembler Directives\n\nThe assembler also supports the following assembler directives:\n\n- `.text`, `.data`\n- `.byte`, `.half`, `.word`, `.dword`\n- `.asciz`\n\n## Supported Branch Prediction Methods\n- `Always Taken`\n- `Always Not Taken`\n- `1-bit Branch Predictor`\n- `2-bit Branch Predictor`\n\n## Usage\n\nTo run asm_to_mc program, follow these steps:\n\n1. **Input File**: Create an input assembly file (e.g., `input.asm`) containing your RISC-V assembly instructions. Each instruction should be on a single line.\n\n2. **Command Line**: Compile and execute the C++ program from the command line. Provide the input assembly file as an argument along with ./a.exe or ./a.out.\n\n3. **Output**: The program will create a separate file named `input.mc`, which contains the parsed assembly language instructions converted into machine language in hexadecimal form.\n\nTo run branch_prediction program, follow these steps:\n\n1. **Input File**: Create an input assembly file (e.g., `input.asm`) containing your TRACE of RISC-V assembly instructions. Each instruction should be on a single line.\n\n2. **Command Line**: Compile and execute the C++ program from the command line. Provide the input assembly file as an argument along with ./a.exe or ./a.out.\n\n3. **Output**: The program will create 3 separate files named `input_OutputBTB.txt`, `input_OutputHT.txt`,`input_OuputAccuracy.txt` which contains Branch Target Buffer, History Table, Accuracy of 4 methods respectively.\n\n## Example for asm_to_mc\n\nHere's an example of an input assembly file (`input.asm`):\n\n```assembly\n.text\naddi x1 x0 10\naddi x2 x1 20\n#This is a comment\nsw x2 0(x1)\n.data\na : .byte 1,2,3\nb : .half 2\nc : .word 0xA2,45\nd : .dword 4\ne : .asciiz \"Hello, World!\"\n```\n\nRunning the program with this input:\n\n```machine code\n0x 0x00A00093\n0x4 0x01408113\n0x8 0x0020A023\n\n\n------------------------DATA--------------------------\n0x10000000 01\n0x10000001 02\n0x10000002 03\n0x10000003 02\n0x10000004 00\n0x10000005 A2\n0x10000006 00\n0x10000007 00\n0x10000008 00\n0x10000009 2D\n0x1000000A 00\n0x1000000B 00\n0x1000000C 00\n0x1000000D 04\n0x1000000E 00\n0x1000000F 00\n0x10000010 00\n0x10000011 00\n0x10000012 00\n0x10000013 00\n0x10000014 00\n0x10000015 48\n0x10000016 65\n0x10000017 6C\n0x10000018 6C\n0x10000019 6F\n0x1000001A 20\n0x1000001B 57\n0x1000001C 6F\n0x1000001D 72\n0x1000001E 6C\n0x1000001F 64\n0x10000020 21\n0x10000021 00\n```\n\nWill generate an output file (`input.mc`) containing the machine language code.\n\n## Example for branch_prediction\n\nHere's an example of an input assembly file (`input.asm`):\n\n```assembly\ncore   0: 0x8000c81c (0x00150513) addi    a0, a0, 1\ncore   0: 0x8000c820 (0xfff5c703) lbu     a4, -1(a1)\ncore   0: 0x8000c824 (0x00078863) beqz    a5, pc + 16\ncore   0: 0x8000c828 (0xfee786e3) beq     a5, a4, pc - 20\ncore   0: 0x8000c814 (0x00054783) lbu     a5, 0(a0)\ncore   0: 0x8000c818 (0x00158593) addi    a1, a1, 1\ncore   0: 0x8000c81c (0x00150513) addi    a0, a0, 1\ncore   0: 0x8000c820 (0xfff5c703) lbu     a4, -1(a1)\ncore   0: 0x8000c824 (0x00078863) beqz    a5, pc + 16\ncore   0: 0x8000c828 (0xfee786e3) beq     a5, a4, pc - 20\ncore   0: 0x8000c82c (0x40e78533) sub     a0, a5, a4\ncore   0: 0x8000c830 (0x00008067) ret\ncore   0: 0x80005b98 (0x02051663) bnez    a0, pc + 44\ncore   0: 0x80005bc4 (0x003c0c13) addi    s8, s8, 3\ncore   0: 0x80005bc8 (0x41fc5793) srai    a5, s8, 31\ncore   0: 0x80005bcc (0x0037f793) andi    a5, a5, 3\ncore   0: 0x80005bd0 (0x018787b3) add     a5, a5, s8\ncore   0: 0x80005bd4 (0x004b2703) lw      a4, 4(s6)\n```\nRunning the program with this input will generate three files:\n\n`input_OutputBTB.txt`\n```.txt\n\n-----------------------BRANCH TARGET BUFFER-----------------------\n\nCurrent PC: 0x8000c824 Target PC: 0x8000c834 MISS\nCurrent PC: 0x8000c828 Target PC: 0x8000c814 HIT\nCurrent PC: 0x8000c824 Target PC: 0x8000c834 MISS\nCurrent PC: 0x8000c828 Target PC: 0x8000c814 MISS\nCurrent PC: 0x80005b98 Target PC: 0x80005bc4 HIT\n\n-------------------------------------------------------------------\n\n```\n\n`input_OutputHT.txt`\n```.txt\n\n\n-----------------------HISTORY TABLE-------------------------------\n\n0x8000c824\nPredictions of One Bit Predictor =\u003e NT|NT|\nPredictions of Two Bit Predictor =\u003e NT|NT|\nActual Result =\u003e NT|NT|\n-------------------------------------------------------------------\n0x8000c828\nPredictions of One Bit Predictor =\u003e NT|T|\nPredictions of Two Bit Predictor =\u003e NT|T|\nActual Result =\u003e T|NT|\n-------------------------------------------------------------------\n0x80005b98\nPredictions of One Bit Predictor =\u003e NT|\nPredictions of Two Bit Predictor =\u003e NT|\nActual Result =\u003e T|\n-------------------------------------------------------------------\n\n```\n`inputAccuracy.txt`\n```.txt\n\n\n------------------------------ACCURACY-------------------------------------\n\nTotal Prediction of 1-bit Branch Predictor -\u003e 40%\nTotal Prediction of 2-bit Branch Predictor -\u003e 40%\nAccuracy of branch predictor By Always Taken -\u003e 40%\nAccuracy of branch predictor By Always Not Taken -\u003e 60%\n\n\n-------------------------------------------------------------------\n\n```\n\n## Contributors\n\n- [Dhruv Gupta](https://github.com/dhruvgupta2112) - Roll No: 2022CSB1079\n- [Kush Mahajan](https://github.com/kushrm2803) - Roll No: 2022CSB1089\n- [Nishant Patil](https://github.com/Nishant984) - Roll No: 2022CSB1097\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fkushrm2803%2Frisc-v_assembler","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fkushrm2803%2Frisc-v_assembler","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fkushrm2803%2Frisc-v_assembler/lists"}