{"id":21828974,"url":"https://github.com/kyuvi/jrv-asm","last_synced_at":"2026-05-19T15:08:29.399Z","repository":{"id":170460677,"uuid":"592074548","full_name":"Kyuvi/Jrv-asm","owner":"Kyuvi","description":"A Clojure library designed for writing RISC-V assembly in clojure","archived":false,"fork":false,"pushed_at":"2023-01-23T05:56:01.000Z","size":52,"stargazers_count":2,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-01-26T08:41:57.340Z","etag":null,"topics":["assembler","clojure","compiler","lisp","risc-v","risc-v-assembly"],"latest_commit_sha":null,"homepage":"","language":"Clojure","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Kyuvi.png","metadata":{"files":{"readme":"README.org","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-01-22T20:48:51.000Z","updated_at":"2023-07-21T19:16:00.000Z","dependencies_parsed_at":null,"dependency_job_id":"df25ba17-e2ae-4132-a226-19279abfbcd6","html_url":"https://github.com/Kyuvi/Jrv-asm","commit_stats":null,"previous_names":["kyuvi/jrv-asm"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Kyuvi%2FJrv-asm","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Kyuvi%2FJrv-asm/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Kyuvi%2FJrv-asm/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Kyuvi%2FJrv-asm/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Kyuvi","download_url":"https://codeload.github.com/Kyuvi/Jrv-asm/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":244800359,"owners_count":20512453,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembler","clojure","compiler","lisp","risc-v","risc-v-assembly"],"created_at":"2024-11-27T18:19:31.357Z","updated_at":"2026-05-19T15:08:29.370Z","avatar_url":"https://github.com/Kyuvi.png","language":"Clojure","funding_links":[],"categories":[],"sub_categories":[],"readme":" #+TITLE: Clojure RISC-V assembler (jrv-asm)\n # #+STARTUP: content\n\n\nA Clojure library designed for writing RISC-V assembly in clojure\n\nThe main repository is on [[https://codeberg.org/Kyuvi/jrv-asm][Codeberg]]. if you are viewing this anywhere else, it is just a mirror. Please use the [[https://codeberg.org/Kyuvi/jrv-asm][Codeberg]] repository for pull requests and issues. Thank you.\n\n* Description\nA crude but functional implementation of a dynamic [[https://en.wikipedia.org/wiki/Riscv][RISC-V]] assembler in [[https://en.wikipedia.org/wiki/Clojure][Clojure]], Still in a pre-alpha state, pretty much everything is liable to change.\n\nIt currently supports only the 32-bit I and M modules plus the base instructions from the C module and the ZiCSR module including the (proposed?) 32-bit CSR memory map, but has been designed to be extended to support other modules and both 64-bit and 128-bit instruction sets as well.\n\nThese are actually the basic modules/packages to be used to build up an assembler for the instruction set of a processor when needed.\n\n# It is not optimized for using compressed instructions, and when using the \"I-C-32-RV\" module, unless compressed instructions are explicitly used, the compressed instructions are only used for resolved immediates (labels), i.e. compressed instructions will only be used for backward branches if possible.\n\n\n* Syntax and Notation\n** Assembly Related\nAll instructions are clojure functions and therefore need to be surrounded by parenthesis\n\nIt includes some changes to the standard assembly notation and syntax namely....\n- nibble - 4-bit (nibble)\n- byte - 8-bit   (byte)\n- kait - 16-bit  (half word)\n- vait - 32-bit  (word)\n- zait - 64-bit  (double word)\n- yait - 128-bit (quad word) (very likely to change)\n\nThough I will probably use Double and Quad for the floating point module names as the module letters are derived from those.\n\nalso sv/lv (store vait/load vait) are of the form....\n- (sv rs rb imm) ;; sv source-reg base-reg immediate\n- (lv rd rb imm) ;; lv dest-reg base-reg immediate\n\nas are all the other loads and stores (sb,lb, sk/lk, sz/lz).\n\nI personally find it easier to think like this about (modern) assembly code.\n\nAlso Register \"zero\" (x0) is renamed to \"zr\" to avoid confusion with clojures =zero?=\nfunction and its test is =zr?= or =z-reg?=.\n\n\n\n** Clojure Related\n\"and\", \"or\", \"rem\", \"not\", \"dec\" and \"inc\" are prefixed with \"cj-\" within the instruction modules so the original words can comply with the RISC-V standard, I feel this convention should be followed when using this library.\n\n\n* Usage\n\nFIXME\n\n* License\n\nCopyright © 2022 Kyuvi\n\nThis program and the accompanying materials are made available under the\nterms of the GNU General Public License 3.0 or later which is available at\nhttps://www.gnu.org/licenses/gpl-3.0.html\n with the GNU Classpath Exception which is available at https://www.gnu.org/software/classpath/license.html.\n\n\n* Acknowledgments\nThis assembler is based on\n- Andy Hefner's [[https://github.com/ahefner/asm6502][asm-6502]], https://ahefner.livejournal.com/20528.html.\n- Technoblogy's [[https://github.com/technoblogy/lisp-riscv-assembler][RISC-V assembler]], http://www.ulisp.com/show?310Z.\n\nAlso thanks to\n- Andrew Dailey's [[https://github.com/theandrew168/bronzebeard][Bronzebeard project]].\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fkyuvi%2Fjrv-asm","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fkyuvi%2Fjrv-asm","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fkyuvi%2Fjrv-asm/lists"}