{"id":13830148,"url":"https://github.com/lakshmi-sathi/avsdpll_1v8","last_synced_at":"2025-07-09T11:32:23.065Z","repository":{"id":62977814,"uuid":"307860553","full_name":"lakshmi-sathi/avsdpll_1v8","owner":"lakshmi-sathi","description":"8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.","archived":false,"fork":false,"pushed_at":"2021-07-31T16:44:18.000Z","size":26481,"stargazers_count":108,"open_issues_count":1,"forks_count":41,"subscribers_count":13,"default_branch":"main","last_synced_at":"2024-11-20T12:09:36.705Z","etag":null,"topics":["analog-circuit","asic","charge-pump","clock-multiplier","ic","intellectual-property","manufacturable","phase-detector","pll","rtl2gds"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/lakshmi-sathi.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-10-28T00:13:31.000Z","updated_at":"2024-10-29T13:42:02.000Z","dependencies_parsed_at":"2022-11-10T06:52:14.572Z","dependency_job_id":null,"html_url":"https://github.com/lakshmi-sathi/avsdpll_1v8","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/lakshmi-sathi/avsdpll_1v8","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lakshmi-sathi%2Favsdpll_1v8","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lakshmi-sathi%2Favsdpll_1v8/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lakshmi-sathi%2Favsdpll_1v8/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lakshmi-sathi%2Favsdpll_1v8/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/lakshmi-sathi","download_url":"https://codeload.github.com/lakshmi-sathi/avsdpll_1v8/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/lakshmi-sathi%2Favsdpll_1v8/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":264450556,"owners_count":23610194,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["analog-circuit","asic","charge-pump","clock-multiplier","ic","intellectual-property","manufacturable","phase-detector","pll","rtl2gds"],"created_at":"2024-08-04T10:00:56.571Z","updated_at":"2025-07-09T11:32:18.056Z","avatar_url":"https://github.com/lakshmi-sathi.png","language":null,"funding_links":[],"categories":["Analog and Analog Mixed Signals (AMS)"],"sub_categories":["PLL/DLL"],"readme":"# 130nm PLL Clock Multiplier IP\n8x PLL Clock Multiplier IP on the Google-Skywater 130nm node.\n\nTested through spice simulations on skywater \u003cb\u003e130nm tt corner at room termperature\u003c/b\u003e\n\nGenerates 8x Multiplied Clock\n\n\u003cb\u003e Pre-Layout: \u003c/b\u003e \u003cbr\u003e\n\nFrequency Obtained for 5Mhz input: \u0026nbsp;\u0026nbsp;\u0026nbsp;40MHz \u003cbr\u003e\nFrequency Obtained for 12.5Mhz input: \u0026nbsp;\u0026nbsp;\u0026nbsp;100MHz\n\nDuty Cycle obtained: \u0026nbsp;\u0026nbsp;\u0026nbsp;46% at 40MHz and 40.6% at 100MHz\n\nLock-in starts at ~80us for 100MHz and ~120us for 40Mhz\n\n3rd-Order Loop Filter used [c1, c2, c3, r1, r2, r3]: \u0026nbsp;\u0026nbsp;\u0026nbsp;355fF, 350fF, 345fF, 490, 490, 490.\n\n\u003cb\u003e Post-Layout: \u003c/b\u003e \u003cbr\u003e\n\nFrequency Obtained for 5Mhz input: \u0026nbsp;\u0026nbsp;\u0026nbsp;40MHz \u003cbr\u003e\nFrequency Obtained for 12.5Mhz input: \u0026nbsp;\u0026nbsp;\u0026nbsp;100MHz\n\nDuty Cycle obtained: \u0026nbsp;\u0026nbsp;\u0026nbsp;52.7% at 40MHz and 50% at 100MHz\n\nLock-in starts at ~22us for 100MHz and ~37us for 40Mhz\n\n3rd-Order Loop Filter used [c1, c2, c3, r1, r2, r3]: \u0026nbsp;\u0026nbsp;\u0026nbsp;295fF, 300fF, 305fF, 490, 490, 490.\n\n\u003ch2\u003e Contents: \u003c/h2\u003e\n\n1. [Google-SkyWater 130nm PDK](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Google-SkyWater-130nm-PDK-)\n2. [Specifications](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Specifications-)\n3. [Pre-Layout Simulations](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Pre-Layout-Simulations-)\n4. [Layout](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Layout-)\n5. [Post-Layout Simulations](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Post-Layout-Simulations-)\n6. [Instructions](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Instructions-)\n7. [EDA tools used](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-EDA-Tools-Used-)\n8. [Preparing your IP for Tapeout](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Preparing-your-IP-for-Tapeout-)\n9. [References](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-References-)\n10. [Future Scope](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Future-Scope-)\n11. [Acknowlegements](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Acknowledgements-)\n12. [Contact](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/README.md#-Contact-)\n\n\u003ch3\u003e Google-SkyWater 130nm PDK: \u003c/h3\u003e\n\n\u003eThis PLL circuit is built on the [Google-Skywater 130nm](https://github.com/google/skywater-pdk) node. It is a mature 180nm-130nm hybrid technology originally developed internally by Cypress Semiconductor. The SkyWater Open Source PDK is a collaboration between Google and SkyWater Technology Foundry to provide a fully open source Process Design Kit and related resources, which can be used to create manufacturable designs at SkyWater’s facility. \n\n\u003ch3\u003e Specifications \u003c/h3\u003e\n\n| Parameter | Description | min | typ | max | Unit | Conditions |\n| --- | --- | --- | --- | --- | --- | --- |\n| VDD | Digital Supply | - | 1.8 | - | V | T = 27C |\n| F\u003csub\u003eCLKREF\u003c/sub\u003e | Reference | 5 | - | 12.5 | MHz | T = 27C |\n| F\u003csub\u003eCLKOUT\u003c/sub\u003e | Output Clock | 40 | - | 100 | MHz | PLL Mode, T = 27C |\n| F\u003csub\u003eCLKOUT\u003c/sub\u003e | Output Clock | - | - | - | MHz | VCO Mode, T = 27C |\n| J\u003csub\u003eRMS\u003c/sub\u003e | Jitter (rms) | - | - | - | ps | PLL_Mode |\n| DC | Duty Cycle | 52.7 | - | 50 | % | T = 27C | \n| T\u003csub\u003eSET\u003c/sub\u003e | Settling Time | ~37 | - | ~22 | ns | T = 27C |\n| C\u003csub\u003eL\u003c/sub\u003e | Load Capacitance | - | - | - | fF | T = 27C |\n| IDD | Supply Current | - | - | - | fF | T = 27C |\n\n\n\u003ch3\u003e Pre-Layout Simulations \u003c/h3\u003e\n\n\u003ch4\u003e PLL Output (tt, 27degree Celcius): \u003c/h4\u003e\n\n\u003cb\u003e Red: \u003c/b\u003e Reference Clock  \u003cbr\u003e \n\u003cb\u003e Blue: \u003c/b\u003e Output Clock Divided by 8  \u003cbr\u003e\n\u003cb\u003e Yellow: \u003c/b\u003e Down Signal \u003cbr\u003e\n\u003cb\u003e Brown: \u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003e Pink (at top): \u003c/b\u003e ChargePump output \u003cbr\u003e\n\n\u003ch4\u003e 40Mhz Output: \u003c/h4\u003e\n    \n\u003ch4\u003e-Close-up \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/40Mhzzoomin.jpg)\n    \n\u003ch4\u003e-Steady State \u003cbr\u003e\u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/5MhzInputSteadyState.png)\n\u003cb\u003e Blue constantly overlapping Red indicating locked state \u003c/b\u003e\n\n\u003ch4\u003e-Trend \u003cbr\u003e \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/5MhzInputFullPicture.jpg)\n\n\u003cb\u003e100Mhz Output: \u003c/b\u003e\u003cbr\u003e\n\n\u003ch4\u003e-Close-up \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/100Mhzzoomin.jpg)\n\n\u003ch4\u003e-Steady State \u003cbr\u003e\u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/12.5MhzInputSteadyState.jpg)\n\u003cb\u003e Blue constantly overlapping Red indicating lock \u003c/b\u003e\n\n\u003ch4\u003e-Trend \u003cbr\u003e\u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/12.5MhzInputFullPicture.jpg)\n\n\u003cb\u003eOutput Specs:\u003c/b\u003e \u003cbr\u003e\n-Exact 40 Mhz\n![](PreLayout/Specs/Exact40Mhz.jpg)\n\n-Exact 100Mhz\n![](PreLayout/Specs/Exact100Mhz.jpg)\n\n\u003ch4\u003e Phase Frequency Detector 'Up' Signal : \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/PD_PreLay_Up.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Clock 2 \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Clock 1 \u003cbr\u003e\n\u003cb\u003eOrange:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eGreen:\u003c/b\u003e Down Signal\n\n\u003ch4\u003e Phase Frequency Detector 'Down' Signal : \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/PD_PreLay_Down.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Clock 2 \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Clock 1 \u003cbr\u003e\n\u003cb\u003eOrange:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eGreen:\u003c/b\u003e Down Signal\n\n\u003ch4\u003e Charge Pump response to 'Up' signal: \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/CP_PreLay_Charge.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Charge Pump Output Voltage \u003cbr\u003e\n\n\u003ch4\u003e Charge Pump response to 'Down' signal: \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/CP_PreLay_Discharge.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Charge Pump Output Voltage\u003cbr\u003e\n\n\u003ch4\u003e Charge Pump output rise due to charge leakage: \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/CP_PreLay_Leakage.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Charge Pump Output Voltage \u003cbr\u003e\n\u003cb\u003eLeakage:\u003c/b\u003e 40uV increase every 1us \u003cbr\u003e\n\n\u003ch4\u003e Frequency Divider: \u003c/h4\u003e\n\n![](PreLayout/Simulation_Results/FD_PreLay.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Output Clock \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Input Clock \u003cbr\u003e\n\n*These above circuits were custom selected to improve stability and reduce area/power consumption.\n\n\n\u003ch3\u003e Layout \u003c/h3\u003e\n\n\u003ch4\u003e Frequency Divider \u003c/h4\u003e\n\n![](Layout/FD_Layout.jpg)\n\n\u003cb\u003e Area: \u003c/b\u003e 29.92um square\n\n\u003ch4\u003e Phase Frequency Detector \u003c/h4\u003e\n\n![](Layout/PFD_Layout.jpg)\n\n\u003cb\u003e Area: \u003c/b\u003e 49.09um square\n\n\u003ch4\u003e Mux \u003c/h4\u003e\n\n![](Layout/MUX_Layout.jpg)\n\n\u003cb\u003e Area: \u003c/b\u003e 12.12um square\n\n\u003ch4\u003e Charge Pump \u003c/h4\u003e\n\n![](Layout/CP_Layout.jpg)\n\n\u003cb\u003e Area: \u003c/b\u003e 132.29um square\n\n\u003ch4\u003e Voltage Controlled Oscillator \u003c/h4\u003e\n\n![](Layout/VCO_Layout.jpg)\n\n\u003cb\u003e Area: \u003c/b\u003e 57.73um square\n\n\u003ch4\u003e Integrated PLL \u003c/h4\u003e\n\n![](Layout/PLL_Layout.jpg)\n\n\u003cb\u003e Area: \u003c/b\u003e 496.03um square\n\n\n\n\u003ch3\u003e Post-Layout Simulations \u003c/h3\u003e\n\n\u003ch4\u003e PLL Output (tt, 27degree Celcius): \u003c/h4\u003e\n\n\u003cb\u003e Red: \u003c/b\u003e Reference Clock  \u003cbr\u003e\n\u003cb\u003e Blue: \u003c/b\u003e Output Clock Divided by 8  \u003cbr\u003e\n\u003cb\u003e Yellow: \u003c/b\u003e Down Signal \u003cbr\u003e\n\u003cb\u003e Brown: \u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003e Pink (at top): \u003c/b\u003e ChargePump output \u003cbr\u003e\n\n\u003cb\u003e40Mhz Output: \u003c/b\u003e \u003cbr\u003e\n\n\u003ch4\u003e-Close-up \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/PostLay40Mhzzoomin.jpg)\n\u003ch4\u003e-Steady State \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/postlay40mhz295fF.jpg)\n\u003cb\u003e Blue constantly overlapping Red indicating locked state \u003c/b\u003e \u003cbr\u003e\n\n\u003ch4\u003e-Trend \u003cbr\u003e\u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/postlay40mhz295fFfullpicture.jpg)\n\n\u003cb\u003e100Mhz Output:\u003c/b\u003e \u003cbr\u003e \n\u003ch4\u003e-Close-up \u003cbr\u003e\u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/Postlay100Mhzzoomin.jpg)\n\n\u003ch4\u003e-Steady State \u003cbr\u003e\u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/postlay100mhz295fF.jpg)\n\u003cb\u003e Blue constantly overlapping Red indicating locked state \u003c/b\u003e \u003cbr\u003e \n\u003ch4\u003e-Trend\u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/postlay100mhz295fFfullpicture.jpg)\n\n\n\n\n\u003cb\u003eOutput Specs:\u003c/b\u003e \u003cbr\u003e\n-40 Mhz\n![](PostLayout/Specs/PostLay40Mhz.jpg)\n\n-Exact 100Mhz\n![](PostLayout/Specs/PostLayExact100Mhz.jpg)\n\n\u003ch4\u003e Phase Frequency Detector 'Up' Signal : \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/PFD_PostLay_Up.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Clock 1 \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Clock 2 \u003cbr\u003e\n\u003cb\u003eOrange:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eGreen:\u003c/b\u003e Down Signal\n\n\u003ch4\u003e Phase Frequency Detector 'Down' Signal : \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/PFD_PostLay_Down.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Clock1 2 \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Clock 2 \u003cbr\u003e\n\u003cb\u003eOrange:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eGreen:\u003c/b\u003e Down Signal\n\n\u003ch4\u003e Charge Pump response to 'Up' signal: \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/CP_PostLayout_Charge.jpg)\n\n\u003cb\u003eOrange:\u003c/b\u003e Charge Pump Output Voltage \u003cbr\u003e\n\u003cb\u003eRed:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Down Signal\n\n\u003ch4\u003e Charge Pump response to 'Down' signal: \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/CP_PostLayout_Discharge.jpg)\n\n\u003cb\u003eOrange:\u003c/b\u003e Charge Pump Output Voltage \u003cbr\u003e\n\u003cb\u003eRed:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Down Signal\n\n\u003ch4\u003e Charge Pump output rise due to charge leakage: \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/CP_PostLayout_Leakage.jpg)\n\n\u003cb\u003eOrange:\u003c/b\u003e Charge Pump Output Voltage \u003cbr\u003e\n\u003cb\u003eRed:\u003c/b\u003e Up Signal \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Down Signal \u003cbr\u003e\n\u003cb\u003eLeakage:\u003c/b\u003e \u003c 0.05V in 100us \u003cbr\u003e\n\n\u003ch4\u003e Frequency Divider: \u003c/h4\u003e\n\n![](PostLayout/Simulation_Results/FD_PostLay.jpg)\n\n\u003cb\u003eRed:\u003c/b\u003e Input Clock \u003cbr\u003e\n\u003cb\u003eBlue:\u003c/b\u003e Output Clock \u003cbr\u003e\n\n\u003ch3\u003e Instructions \u003c/h3\u003e\n\n\u003ch4\u003e For using magic for layout: \u003c/h4\u003e\n\n* Get magic v8.3.82 or above from [here](http://opencircuitdesign.com/magic) \u003cbr\u003e\n* Place the tech file [sky130.tech](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/sky130.tech) in the folder where you'll be using magic \u003cbr\u003e\n* Open magic using the command:\n    ```magic -T sky130```\n\n\u003ch4\u003e For using ngpice for simulations: \u003c/h4\u003e\n\n* Get ngspice from [here](http://ngspice.sourceforge.net/) or for ubuntu users, just use this command: ```sudo apt-get install ngspice``` \u003cbr\u003e\n* Place the [sky130nm.lib](https://github.com/lakshmi-sathi/avsdpll_1v8/blob/main/sky130nm.lib) file and the Sky130_Primitives folder in the location where you'll be running ngspice \u003cbr\u003e\n* Run the simulation: \n    ```ngspice circuitname.cir``` \n    \n\u003ch3\u003e EDA Tools Used \u003c/h3\u003e\n\n* [kicad](https://kicad.org/) (schematic capture) \u003cbr\u003e\n* [ngspice](http://ngspice.sourceforge.net/download.html) (simulation) \u003cbr\u003e\n* [magic](http://opencircuitdesign.com/magic/) (layout design) \n\n\u003ch3\u003e Preparing your IP for Tapeout \u003c/h3\u003e\n\nFor any design to be tapeout ready there are more requirements than just having a finished and tested IP Layout.\u003cbr\u003e\nFor Example, a proper GPIO (cells that enable the IP to be interfaced with external world) is needed for connecting the IP pins to the package (the final DIP or Surface Mount case in which the IC comes in from the Fab) \u003cbr\u003e\n\nTo meet these requirements either we need to take care of them individually by ourself (which may get complicated and time consuming) or, \u003cbr\u003e\nwe can choose a vehicle for enabling our IP to meet the requirements to go through the fabrication process. \u003cbr\u003e\nHere we will be using [Efabless Caravel SoC template](https://github.com/efabless/caravel) as the Vehicle. \u003cbr\u003e\n\nBefore we start, this is the [datasheet](https://github.com/efabless/caravel/blob/master/doc/caravel_datasheet.pdf) of the Caravel SoC from [Efabless](https://efabless.com/), \u003cbr\u003e\nand these are the parts involved in it: \u003cbr\u003e\n\n![](Images/CaravelSoCTemplate.jpg)\nThe Mega Project Area (MPRJ) or 'user_project_wrapper' or in other words 'the container' is where we will place and route our IP.\n\n\u003ch4\u003e Basic Steps Overview: \u003c/h4\u003e\n\n* Initial setup.\n* Place and Route the IP inside the container (keep in mind to not have any DRCs).\n* Verify Connectivity.\n* Integrate the container onto the Caravel SoC.\n* Check if everything is as expected including DRC (Precheck).\n\nGetting it ready is as direct as this. We will see in detail the steps involved in context of Caravel SoC and Google-Skywater OpenShuttle.\n\n\u003ch4\u003e Steps in Detail: \u003c/h4\u003e\n\n\u003ch5\u003e 1) Initial Setup \u003c/h5\u003e \n\nSteps:\n* Fork and clone Caravel\n* Uncompress files\n* Install PDK\n\n-\u003e Fork and 'git clone' the Caravel SoC. \u003cbr\u003e \u003cbr\u003e\nSelect the 'Fork' option on the top right of the [Caravel Github](https://github.com/efabless/caravel) repo. \u003cbr\u003e\nSpecify a name for your fork and then clone it (somewhere on your system where you want to integrate the design onto the Caravel SoC):\n\u003e git clone \\\u003curl of your fork\\\u003e\n\n![](Images/caravel_repo_root.jpg)\n\u003cbr\u003e\nHere we can see the content of the Caravel Repo. Each type of file is placed in it's respective folder. \u003cbr\u003e\nOur main focus is the 'gds' folder which contains all the Layout GDS files. \u003cbr\u003e \u003cbr\u003e\n\nWe can see that several files have '.gz' extension. All these files are compressed files. This compression is in place to meet the Github size limit on individual files. \u003cbr\u003e\nThey need to be uncompressed for working on them. \u003cbr\u003e\n-\u003e This can be done the right way by moving to the root folder (the folder which is the local clone of the forked caravel repo) and giving:\n\u003e make uncompress\n\nNow we need to setup the [Google-Skywater PDK](https://github.com/google/skywater-pdk) on the machine on which this integration is to be performed. \u003cbr\u003e\n-\u003e The entire PDK installation is provided as a two step process: \u003cbr\u003e\n\u003e export PDK_ROOT=\\\u003clocation where you want to install it\\\u003e \n\n\u0026nbsp;You would want to install it outside the local clone of the caravel repo since finally it has to be pushed back to Github. \u003cbr\u003e\n-\u003e Move to the root folder and give:\n\u003e make pdk\n\nThis downloads and installs the pdks in the location specified earlier (It takes a significant amount of time).\n    \n\u003ch5\u003e 2) Place and Route \u003c/h5\u003e\n\nThere are two ways to place and route:\n* Automatically (Openlane) - commonly used in large digital designs.\n* Manually - good for designs that aren't having too many pins to interface.\n\nHere in context of the PLL IP, we will be proceeding along the Manual method of placing and routing the IP. \u003cbr\u003e\nFor more information on the automatic method follow this [link](https://github.com/efabless/caravel/blob/master/openlane/README.md).\n\nFor placing and routing the IP manually the magic layout tool can be used:\n* export the PDK_ROOT variable with the location of the PDK installation.\n* cd to the 'mag' folder and open magic layout tool (this is since the .magicrc configuration file is in this folder).\n\n  This is how to open magic with the right configuration for Caravel with the installed PDK:\n  ![](Images/opening_magic.jpg)\n  \n* Select File -\u003e Read GDS and open user_project_wrapper.gds from 'gds' folder (this is the container where we are going to place the IP).\n* Select Cell -\u003e Place Instance and select the mag file of the IP you want to insert (this allows you to place your IP inside this container).\n\n![](Images/place_ip.jpg)\n\n![](Images/PLL_in_caravel.jpg)\n\n* After Placing the IP by seeing a location with the right I/O pins, manually route the IP pins to the appropriate pins on the container (refer to the datasheet mentioned earlier). Keep in mind to avoid DRC errors.\n* Select File -\u003e Write GDS and write out the GDS file for the modified container (remember that the final container in which the IP is placed should be named user_project_wrapper.gds and it should be inside 'gds' folder, this is required for the integration step using 'make' to work).\n\n\u003ch5\u003e 3) Verify Connectivity \u003c/h5\u003e\n\nIn context of the a manual connectivity check for it's connectivity to the container pins is performed. You may want to have an automated process if your design has a large number of pins.\u003cbr\u003e\n\nThe connectivity check can be done through the simple yet effective net tracing feature of the magic layout tool:\n* Select any part of the net you wish to trace using the 's' key.\n\nReference net or Input clock net can be seen selected in this image:\n![](Images/selected.jpg)\n\n* Press 's' multiple times to see the net being traced till it's endpoints.\n\n![](Images/net_trace.jpg)\n\nNow the fully highlighted net enables us to see which pin is connected where.\u003cbr\u003e\nThis way we can do the same for all nets interfacing the IP to the container to verify the connectivity.\n\n\u003ch5\u003e 4) Integrating Container to Caravel SoC \u003c/h5\u003e\n\nThe Caravel Repo uses a simple 'make' based method to integrate the container onto the Caravel SoC. \u003cbr\u003e\n\nAll that needs to be done, once all the place, route and verification is completed, \u003cbr\u003e\nis to move to the root folder (the folder which is the local clone of the forked caravel repo) and, \u003cbr\u003e\ngive the 'make' command. This integrates the container onto the Caravel SoC (takes about 10-15mins usually). \u003cbr\u003e\n\nWe can see that in 'gds' folder a 'caravel.gds' file is generated. \u003cbr\u003e\nThis is the final gds file which is to be used by the Fab for fabricating the IC.\n\n\u003ch5\u003e 5) Precheck \u003c/h5\u003e\n\nThe precheck is provided as a [separate repo](https://github.com/efabless/open_mpw_precheck) by Efabless.\nThis was the precheck for Google-Skywater-Efabless open MPW shuttle 2020, on which this guide will be based. It would be different for different tapeout runs and you would need to find the one for the specific tapeout run that you are tagetting.\n\nEfabless Caravel Precheck is designed to run on docker (a container for software, kind of like Virtual Machine). Follow this [link](https://docs.docker.com/engine/install/ubuntu/) to know how to install docker. \u003cbr\u003e\n\nClone the Efabless precheck repo and follow these steps to run the precheck on your finished Caravel:\n* Fetch their open_mpw_precheck docker\n\n``` cd dependencies\nsh build-docker.sh\ndocker pull efabless/open_mpw_precheck:latest\n```\n\n* Load the precheck docker (assuming the PDK is already installed from the Caravel repo as mentioned earlier in the initial setup step)\n```\nexport PDK_ROOT=\u003c location where the PDK was installed \u003e\nexport TARGET_PATH=\u003c location where you have the forked and cloned Caravel repo where the completed caravel exists \u003e\ndocker run -it -v $(pwd):/usr/local/bin -v $TARGET_PATH:$TARGET_PATH -v $PDK_ROOT:$PDK_ROOT -e TARGET_PATH=$TARGET_PATH -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) efabless/open_mpw_precheck:latest\n```\n\nAfter docker loads you should see 'bash $' indication on the terminal.\n\n* Run the precheck\n```\npython3 open_mpw_prechecker.py [-h] --target_path \u003c the target path given earlier \u003e --pdk_root \u003c the pdk location given earlier \u003e --waive_fuzzy_checks\n```\n\nThis image shows how to load docker and run the precheck:\n![](Images/run_precheck.jpg)\n\nThis should run the precheck and tell you which of the checks failed, which passed and whether there are any DRC violations.\u003cbr\u003e\n\n![](Images/precheck.jpg)\n\nContact the organisation facilitating the tapeout run you are interested in and enquire what other steps are required to ensure tapeout readiness.\u003cbr\u003e\u003cbr\u003e\nAnd you are done! \u003cbr\u003e\n\n\u003ch5\u003e Fun Fact! \u003c/h5\u003e\nThe Google-Skywater openshuttle 2020, was the first of its kind where any individual could have his/her open-source IP design fabricated and delivered for free (costs sponsored by Google), which would otherwise be in many thousands of US dollars. This PLL IP fabrication was enabled through it.\n\n![](Images/open_mpw_shuttle.jpg)\n\n\u003ch3\u003e References \u003c/h3\u003e\n\n\u003cb\u003e[1]\u003c/b\u003e K.K. Abdul Majeed, Binsu J. Kailath, A Novel Phase Frequency Detector for a High Frequency PLL Design, Procedia Engineering, Volume 64, 2013, Pages 377-384, ISSN 1877-7058,\ndoi: 10.1016/j.proeng.2013.09.110. \u003cbr\u003e \u003cbr\u003e \n\u003cb\u003e[2]\u003c/b\u003e X. Liu and A. N. Willson, \"A pA-leakage CMOS charge pump for low-supply PLLs,\" 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, Seattle, WA, 2010, pp. 1037-1040, doi: 10.1109/MWSCAS.2010.5548821. \u003cbr\u003e \u003cbr\u003e \n\u003cb\u003e[3]\u003c/b\u003e Suman, Shruti \u0026 Sharma, Krishna. (2018). An Improved Performance Ring VCO: Analysis and Design. Ciência e Técnica Vitivinícola. 33. 254-0223. \u003cbr\u003e \u003cbr\u003e \n\u003cb\u003e[4]\u003c/b\u003e Karbalaei Mohammad Ali, M., Hashemipour, O. A simple and high performance charge pump based on the self-cascode transistor. Analog Integr Circ Sig Process 100, 633–638 (2019). doi: 10.1007/s10470-019-01478-y \u003cbr\u003e \u003cbr\u003e \n\u003cb\u003e[5]\u003c/b\u003e Y. -. Choi and D. -. Han, \"Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop,\" in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 10, pp. 1022-1025, Oct. 2006, doi: 10.1109/TCSII.2006.882122. \u003cbr\u003e \u003cbr\u003e \n\u003cb\u003e[6]\u003c/b\u003e Agrawal, Abhishek and Nikhil Saxena. “Comparative Analysis of High Speed FBB TSPC and E-TSPC Frequency Divider at 32 nm CMOS process,” International Journal of Trend in Research and Development (2017), Volume 4(1), ISSN: 2394-9333.\n\n\n\u003ch3\u003e Future Scope \u003c/h3\u003e \n\n* Incorporation of Trimmer Codes.\n* Incorporation of PVT compensation circuit.\n\n\u003ch3\u003e Acknowledgements \u003c/h3\u003e\n\n* I thank Mr. Kunal Ghosh, co-founder [VSD](https://www.vlsisystemdesign.com/), for providing me the opportunity to  work on this wonderful project.\n* I thank [Google](https://github.com/google), [Skywater](https://www.skywatertechnology.com/) and [Efabless](https://efabless.com/) for bringing this wonderful [opportunity](https://www.skywatertechnology.com/press-releases/google-partners-with-skywater-and-efabless-to-enable-open-source-manufacturing-of-custom-asics/) to the world and making this project tapeout possible.\n\n\u003ch3\u003e Contact \u003c/h3\u003e\n\n* Lakshmi S (Author), MS ECE - lakshmi.sathi96@gmail.com\n* Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - kunalghosh@gmail.com\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flakshmi-sathi%2Favsdpll_1v8","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flakshmi-sathi%2Favsdpll_1v8","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flakshmi-sathi%2Favsdpll_1v8/lists"}