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[Files and folders](#files-and-folders)\n  - [Basic vhdl tutorial with ghdl](#basic-vhdl-tutorial-with-ghdl)\n  - [Each design should be composed of two .vhdl files initially:](#each-design-should-be-composed-of-two-vhdl-files-initially)\n  - [Casual convention:](#casual-convention)\n    - [Development process:](#development-process)\n\n\n## Files and folders\n - `counters`\n   - ring_counter.vhdl - a simple ring counter -- a counter that shifts a single bit through a series of flip-flops\n   - counter.vhdl - a simple counter\n - `encoders`\n   - `grey.vhdl` - a simple grey encoder\n   - `one_hot.vhdl` - a simple one hot encoder\n - `machines`\n   - `compar_fsm.vhdl` - a simple finite state machine that compares two numbers\n   - `seq_det.vhdl` - a simple sequence detector\n   - `code_det.vhdl` - a simple code detector\n - `memory`\n   - `dram.vhdl` \n   - `hist.vhdl` \n   - `lifovhdl`  \n - `multiplexers_registers`\n    - `barrel.vhdl` - a simple barrel shifter\n    - `piso.vhdl` - a parallel-in serial-out shift register\n    - `sipo.vhdl` - a serial-in parallel-out shift register\n    - `reg_adder.vhdl` - a simple register adder\n\n## Basic vhdl tutorial with ghdl\n\nInstall ghdl - open source vhdl simulation tool (works both on Linux and Windows) using link below or try fetching it via your system installer: http://ghdl.free.fr/  \nand gtkwave to view simulation runs: http://gtkwave.sourceforge.net/  \nAlternatively, you can use any other waveform viewer, for instance: http://raczben.pythonanywhere.com/#\n\n\n## Each design should be composed of two .vhdl files initially:\n1. Your main design declaration\n2. Your testbench for design (i.e. the testing setup, allows to view how signals are processed by main design)\n\n## Casual convention:\n```sh\ncomponent.vhdl - main design  \ncomponent_tb.vhdl - testbench  \n```\n\n### Development process:\n\n1. Write your design e.g. in `component.vhdl`\n2. Let ghdl check for syntax:  \n    use : \n    ```sh\n    (~) ghdl -a component.vhdl\n    ```\n\n3. Build .o by typing  \n    ```sh\n    (~) ghdl -e component\n    ```\n4. Write your testbench  \n    e.g. `component_tb.vhdl`\n5. Check testbench for syntax  \n    ```sh\n    (~) ghdl -a component_tb.vhdl\n    ```\n6. Create .o file  \n   ```sh\n    (~) ghdl -e component_tb\n    ```\n7. Run your testbench for a limited time!, and save simulation output (wavefile .vcd)  \n    e.g. ~ghdl -r component_tb --stop-time=120ns --vcd=component.vcd\n8.  View the results\n    ```sh\n    (~)  gtkwave component.vcd  \n    ```\n    or upload to online viewer: `http://raczben.pythonanywhere.com/#`.\n\nRemeber to drag signals into viewing pane and adjust the time scale\n\n## To automate the debugging process, use Makefile included in the directory. \n\nJust add the new .vhdl files and objects to corresponding fields using \"\\\" and run analysis with:  \n```sh\n(~) make anal name=component_name\n```\nto clean the .o, .cf, work and other redundant files (except testbench and design file) run:  \n```sh   \n(~) make clean  \n```\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flemurpwned%2Fclassic-fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flemurpwned%2Fclassic-fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flemurpwned%2Fclassic-fpga/lists"}