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discretize\n\n\u003e [!WARNING]\n\u003e This is still in the early alpha stages, the output logic, netlist, and\n\u003e KiCad files may be sub-optimal, or require an obscene number of devices.\n\ndiscretize is a set of a [Yosys] plugin, [`synth_discretize`], and a set of [utility scripts](./contrib/) for synthesizing an HDL design into a netlist of discrete [MOSFET]s and generating a [KiCad] netlist and schematic for the design.\n\n## How It Works\n\nTODO\n\n\n## Usage\n\nTo convert an HDL design into it's discrete representation [`synth_discretize`] is used like any other [Yosys] pass to apply technology mapping and optimization onto the design, converting it to an equivalent design made out of [MOSFET]s\n\nFor example, the following yosys script will synthesize the [`counter.v`](./tests/counter.v) file\ninto a discrete netlist, and then dump the statistics and generated module.\n\n```\nplugin -i ./build/src/techlib/synth_discretize.so\nread_verilog ./tests/counter.v\nsynth_discretize -techlib ./src/techlib\ntee -o counter.stat.json stat -json\nwrite_verilog -noexpr counter.discrete.v\n```\n\nYou can run that like `$ yosys -s counter.ys`, and you should two files `counter.stats.json` and `counter.discrete.v`.\n\nThe first file, `counter.stats.json` describes the design statistics, in the case of the example above it would be something like:\n\n```json\n\"design\": {\n  \"num_wires\":         826,\n  \"num_wire_bits\":     2066,\n  \"num_pub_wires\":     5,\n  \"num_pub_wire_bits\": 19,\n  \"num_memories\":      0,\n  \"num_memory_bits\":   0,\n  \"num_processes\":     0,\n  \"num_cells\":         478,\n  \"num_cells_by_type\": {\n      \"$_SDFF_PN0_\": 8,\n      \"GND\": 1,\n      \"NFET\": 246,\n      \"PFET\": 222,\n      \"VCC\": 1\n  }\n}\n```\n\nNotice two cells called `GND` and `VCC` those are added to ensure that constant highs and lows are tied properly, in a fully implemented design, those would be a ground pour and a power pour on the board.\n\nThe next file, `counter.discrete.v` contains the dumped verilog module with all of the logic broken into wires and instances of `PFET`'s or `NFET`s.\n\n\n## Configuring and Building\n\nThe following steps describe how to build discretize, it should be consistent for Linux, macOS, and Windows, but macOS and Windows remain untested.\n\n**NOTE:** The minimum C++ standard to build discretize is C++17.\n\n### Prerequisites\n\nTo build discretize, ensure you have the following build time dependencies:\n * git\n * meson\n * ninja\n * g++ \u003e= 11 or clang++ \u003e= 11\n * python \u003e= 3.9\n * yosys \u003e= 0.28\n\n\n### Configuring\n\nYou can build discretize with the default options, all of which can be found in [`meson_options.txt`](meson_options.txt). You can change these by specifying `-D\u003cOPTION_NAME\u003e=\u003cVALUE\u003e` at initial meson invocation time, or with `meson configure` in the build directory post initial configure.\n\nTo change the install prefix, which is `/usr/local` by default ensure to pass `--prefix \u003cPREFIX\u003e` when running meson for the first time.\n\nIn either case, simply running `meson build` from the root of the repository will be sufficient and place all of the build files in the `build` subdirectory.\n\n### Building\n\nOnce you have configured discretize appropriately, to simply build and install simply run the following:\n\n```\n$ ninja -C build\n$ ninja -C build test # Optional: Run Tests\n$ ninja -C build install\n```\n\nThis will build and install discretize into the default prefix which is `/usr/local`, to change that see the configuration steps above.\n\n### Notes to Package Maintainers\n\nIf you are building discretize for inclusion in a distributions package system then ensure to set `DESTDIR` prior to running meson install.\n\nThere is also a `bugreport_url` configuration option that is set to this repositories issues tracker by default, it is recommended to change it to your distributions bug tracking page.\n\n## License\n\nDiscretize is licensed under the [BSD-3-Clause](https://spdx.org/licenses/BSD-3-Clause.html), the full text of which can be found in the [LICENSE](LICENSE) file.\n\n\n[yosys]: https://github.com/YosysHQ/yosys\n[kicad]: https://www.kicad.org/\n\n[`synth_discretize`]: ./src/techlib\n[`write_kicad`]: https://github.com/lethalbit/write_kicad\n[MOSFET]: https://en.wikipedia.org/wiki/MOSFET\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flethalbit%2Fdiscretize","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Flethalbit%2Fdiscretize","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Flethalbit%2Fdiscretize/lists"}